Hi,
Ther seem to be some difference between Table 8: pin assignment and the Description in capter 5.7 I2C
In the description I2C_CAM0 and I2C_CAM1 are connected via a MUX to 1 internal I2C, in the Table 8 they are indipendend I2C’s.
Also Table 10 seem to have some errors (like for example P105 Soc Signal: Not Connected but ALT1: i2c4.SDA).
Can You correct the Table 8 (and Table 10?).
Hi, I’m the Toradex AI Assistant.
I might make mistakes or occasionally get you wrong. Our support team will step in if needed.
I’d be glad to help clarify this! To provide you with accurate information about the specific tables and I2C configuration you’re referring to, could you let me know which hardware module and OS version you are using? (1)
The details you’re mentioning about Table 8 pin assignments and I2C_CAM0/I2C_CAM1 configurations can vary significantly between different Toradex modules. Common platforms include:
Hardware: Verdin i.MX8M Plus, Verdin AM62, Aquila AM69, Apalis i.MX8QP, Colibri i.MX8X, Ivy Carrier Board, Ixora Carrier Board, Mallow Carrier Board
OS: Yocto 7.2.0, Torizon 6.8.2, Torizon OS 6, BSP 7, BSP 6, Torizon OS 7.2.0-build.13
You can also use the tdx-info command to get detailed information about your setup. More details are available at: Getting Device Information with Tdx-Info | Toradex Developer Center
Once I know your specific module and OS version, I can provide accurate information about the pin assignments and I2C configurations from the correct datasheet.
Best regards, Toradex AI Assistant.
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The Module is the SMARC iMX95 HW revision 1.1 Datasheet, Documente revision 1.0
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Thank you for specifying the SMARC iMX95 module! I can see you’re referring to documentation inconsistencies in the SMARC iMX95 datasheet.
Based on the available documentation sources, I have access to the SMARC iMX95 V1.0 Preliminary datasheet (1)(2)(3), but I don’t have access to the specific sections you mentioned (Chapter 5.7 I2C description or the complete Table 8 and Table 10 with the discrepancies you’re highlighting).
The pin assignment information I can see shows various GPIO and interface configurations (1), but the specific I2C_CAM0/I2C_CAM1 MUX configuration details and the P105 signal discrepancy you mentioned are not visible in the sections I have access to.
Since you’ve identified specific documentation errors in:
I recommend reporting these documentation discrepancies directly through the official channels. You may find relevant discussions on the Toradex Community by searching for “SMARC iMX95 datasheet” or “documentation errors.”
For the most accurate and up-to-date information about the SMARC iMX95 pin assignments and I2C configurations, please refer to the complete datasheet or contact Toradex technical support to ensure these documentation issues are addressed in future revisions.
Best regards, Toradex AI Assistant.
Did you like my answer?
If I answered your question, please tick the “Solution” checkbox.
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We checked with our documentation team, and they said that the chapter 5.7 and Table 8 details are correct and reflect two hardware variants:
Besides, you were right about Table 10, and they will fix it as soon as possible.
Thanks for the feedback!
Best regards.
Ok, but I still don’t understand Table 8:
According to this I2C_CAM0 is Using GPIO_IO30 and 31 (corrisponding to I2c4 of the SoC) while I2C_CAM1 uses GPIO_IO08 and 09 (corrisponding to i2c7 of the SoC).
But Capter 5.7.1 says that when the I2C Switch is obmitted, then both I2C’s are connected together to the same SoC i2c (occording to the Block diagram this should be i2c7).
Without the I2C switch, you won’t have I2C_CAM0, only I2C_CAM1. With the switch, I2C7 turns into two I2Cs (I2C_CAM0 and I2C_CAM1).
The block diagram shows the variant with the I2C switch.
Best regards.
OK, so I can presume that i2c4 on I2C_CAM0 is an artefact from the previous HW Version, and is not present on the Connector. (I2c4 is used only internal of the SoM)
This means that when I need can5 of the SoC, I have to order ther version with out I2c Switch, and use S1 and S2.
Or if I use the “default” version (with the I2C switch), then can5 must be on S139 and S140 (where I2C_LCD is).
For me this is still confusing. I whould like to have all 5 Can Controllers and at least 3x I2C controller (if possible on the standard Pin’s).
Martin
With the switch, I2C7 (from the i.MX95 SoC) becomes two I2Cs (I2C_CAM0 and I2C_CAM1). These I2Cs are connected to the SMARC connector and available in the carrier board.
If you get the version without the switch, you’ll have only the I2C7 available.
In the block diagram section below, you can check what I explained:
Summarizing, you can have 5 CAN controllers:
Also, you will still have these I2Cs:
Best regards.
best regards
Martin
Hi Lucas,
Sorry but I don’t understand how You can have the CAN interface on the pins You are mentioning.
The only pins that I can understand are P136 and P137 (standards SER2_TX, SER2_RX) thy can be uses for can4 (iMX95 numbering).
According to Table 9.
- P001 is OK as can3_tx
I Have the following setup:
SMARC Pin number SMARC Signal iMX Soc Ball iMX peripheral
P143 / P144 CAN0 F46 / G45 can1
P145 / P146 CAN1 T52 / U49 can2
P121 / P122 I2C_PM V44 / U51 can3
P136 / P137 SER2 K46 / L45 can4
S139 / S140 I2C_LCD T46 / T44 can5
This leaves me with only two I2C (when not using the switch):
S048 / S049 I2C_GP
S001 / S002 I2C_CAM1 (I2C_CAM0 is not connected?)
I think I can live with this.
Can You confirm my configuration?
P.s. is it possible to have a corrected Table 9 (and Table 10)?
Best regards
Martin
In Table 10, the alternative function ALT2 of P5 is can3.RX.
Also, you are right about S139 and S140, sorry for the mistake.
If this works for you, the setup is correct. But also, please check again about P5 and the setup I suggested before.
Best regards.
Hi Lucas,
Yes I see that P5 has can3.RX as ALT2, but in Table 8 P005 is marked (in red) as “3.3V IO Level Shifter Output”, can I asume that this is an error, and that P005 is directly connected to AJ21 of the SOC?
Best regards
Martin
