Set lvds display to single channel at booting stage

Dear Sir,

Currently Im using lvds-display-single-channel script to set my lvds display to single channel mode. Its working fine, but I want to set a splash screen during booting, so I need a lvds display working properly during booting. Is there a way to set a single channel mode in earlier stage? my vidargs are set as follows: vidargs ‘video=tegrafb0:1024x768R-16@60’

Best regards,
Kamil

You should be able to do similar configuration as that lvds-display-single-channel script does from within U-Boot e.g. as explained in the following article on our developer website.

So I have lvds-display-setting script file as follows:

echo high > /sys/class/gpio/gpio216/direction
echo low  > /sys/class/gpio/gpio219/direction
echo high  > /sys/class/gpio/gpio222/direction
echo low  > /sys/class/gpio/gpio223/direction
echo high  > /sys/class/gpio/gpio226/direction
echo high  > /sys/class/gpio/gpio225/direction
echo high  > /sys/class/gpio/gpio221/direction
echo high  > /sys/class/gpio/gpio220/direction

And u-boot setting as follows:

vidargs=video=tegrafb0:1024x768R-16@60
lvds_setting=gpio set 216; gpio set 222; gpio set 226; gpio set 225; gpio set 221; gpio set 220
bootcmd=run lvds_setting;run emmcboot; echo; echo emmcboot failed; run sdboot; echo; echo sdboot failed; run usbboot; echo; echo usbboot failed; run nfsboot; echo; echo nfsboot failed
setup=setenv setupargs gpt gpt_sector=${gptoffset} igb_mac=${ethaddr} no_console_suspend=1 console=tty1 console=ttyS0,${baudrate}n8 debug_uartport=lsport,0 ${memargs} fbcon=map:0

during boot:

U-Boot 2015.04 (Jun 28 2016 - 13:19:53)

TEGRA30
DRAM:  2 GiB
MMC:   Tegra SD/MMC: 0, Tegra SD/MMC: 1, Tegra SD/MMC: 2
tegra-pcie: PCI regions:
tegra-pcie:   I/O: 0x2000000-0x2010000
tegra-pcie:   non-prefetchable memory: 0x20000000-0x30000000
tegra-pcie:   prefetchable memory: 0x30000000-0x40000000
tegra-pcie: 4x1, 1x2 configuration
tegra-pcie: probing port 2, using 1 lanes
In:    serial
Out:   lcd
Err:   lcd
Model: Toradex Apalis T30 2GB V1.0E, Serial# 02650923
Net:   e1000: no NVM
e1000#0
Hit any key to stop autoboot:  0 
gpio: pin 216 (gpio 216) value is 1
gpio: pin 222 (gpio 222) value is 1
gpio: pin 226 (gpio 226) value is 1
gpio: pin 225 (gpio 225) value is 1
gpio: pin 221 (gpio 221) value is 1
gpio: pin 220 (gpio 220) value is 1
Saving Environment to MMC...
Writing to MMC(0)... done
Booting from internal eMMC chip...
reading tegra30-apalis-eval.dtb
** Unable to read file tegra30-apalis-eval.dtb **
reading uImage
4402720 bytes read in 122 ms (34.4 MiB/s)
## Booting kernel from Legacy Image at 81000000 ...
   Image Name:   Linux-3.1.10-gb496d09
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    4402656 Bytes = 4.2 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...

but lvds is still not working during boot. It starts working together with X server. Any sugestions what can be wrong?

Sorry, I forgot to mention you having to set the proper resolution and display timing as well here and re-compile U-Boot as explained here.

So I have followed your instruction and can see proper screen from the computer start, up to the command “starting kernel…”. Just after command “starting kernel…” arise screen stops working properly up to the X server start.

My configurations is:

cat /proc/cmdline 
core_edp_mv=1300 usb_high_speed=1 ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 rootwait gpt gpt_sector= igb_mac=00:14:2d:29:3a:e7 no_console_suspend=1 console=tty1 console=ttyS0,115200n8 debug_uartport=lsport,0 vmalloc=256M mem=2035M@2048M fbmem=12M@4083M fbcon=map:0 video=tegrafb0:1024x768-16@60


u-boot-toradex# git diff
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index be4f4d6..983c7bb 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -300,14 +300,14 @@
 
        lcd_panel: panel {
                clock = <25175000>;
-               xres = <640>;
-               yres = <480>;
-               left-margin = <48>;     /* horizontal back porch */
-               right-margin = <16>;    /* horizontal front porch */
-               hsync-len = <96>;
-               lower-margin = <11>;    /* vertical front porch */
-               upper-margin = <31>;    /* vertical back porch */
-               vsync-len = <2>;
+               xres = <1024>;
+               yres = <768>;
+               left-margin = <160>;    /* horizontal back porch */
+               right-margin = <24>;    /* horizontal front porch */
+               hsync-len = <136>;
+               lower-margin = <29>;    /* vertical front porch */
+               upper-margin = <3>;     /* vertical back porch */
+               vsync-len = <6>;
                hsync-active-high;
                vsync-active-high;
                nvidia,bits-per-pixel = <16>;


Linux ED4012 3.1.10-gd2f0387 #2 SMP PREEMPT Fri Dec 2 10:03:18 CET 2016 armv7l GNU/Linux

Any ideas what else can be wrong?

I have made some tests and looks like kernel resets GPIO settings. I tried to add to the kernel:

diff --git a/arch/arm/mach-tegra/board-apalis_t30.c b/arch/arm/mach-tegra/board-apalis_t30.c
index 037db97..dbdbe8b 100644
--- a/arch/arm/mach-tegra/board-apalis_t30.c
+++ b/arch/arm/mach-tegra/board-apalis_t30.c
@@ -520,6 +520,16 @@ static void apalis_t30_gpio_init(void)
                        gpio_export(apalis_t30_gpios[i].gpio, true);
                }
        }
+
+       //setting up lvds gpio values
+       gpio_set_value(LVDS_MODE, 1);
+       gpio_set_value(LVDS_6B_8B_N, 0);
+       gpio_set_value(LVDS_OE, 1);
+       gpio_set_value(LVDS_PDWN_N, 1);
+       gpio_set_value(LVDS_R_F_N, 1);
+       gpio_set_value(LVDS_MAP, 0);
+       gpio_set_value(LVDS_RS, 1);
+       gpio_set_value(LVDS_DDR_N, 1);

but with no success. Any sugestions?

changed to

        //setting up lvds gpio values
        gpio_direction_output(LVDS_MODE, 1);
        gpio_direction_output(LVDS_6B_8B_N, 0);
        gpio_direction_output(LVDS_OE, 1);
        gpio_direction_output(LVDS_PDWN_N, 1);
        gpio_direction_output(LVDS_R_F_N, 1);
        gpio_direction_output(LVDS_MAP, 0);
        gpio_direction_output(LVDS_RS, 1);
        gpio_direction_output(LVDS_DDR_N, 1);

and the result is:

  1. screen is OK during u-boot stage,
  2. becomes bad for few seconds when starting kernel… log arise,
  3. And then becomes OK.

Is it any way to avoid this gap in screen gpio configuration during kernel boot? Why kernel resets gpio settings from u-boot?

What exactly do you mean by “screen is OK” resp. “becomes bad”?

I guess an OK screen may require several things to be configured properly:

  • display resolution/timing (U-Boot device tree vs. Linux kernel boot argument vidargs)
  • frame buffer content (U-Boot vs. Linux kernel)
  • LVDS transceiver GPIO configuration (U-Boot vs. Linux kernel)

Screen OK means that screen works good, properly displaying data during boot. When the starting kernel… log arises on the screen, screen stops display data and becomes unreadable flooded with strange colors like bad single/dual channel is set. And finally, after a few seconds (2-3 seconds) screen starts to display proper data again during kernel boot. It looks like the GPIO set is correct during u-boot and properly displays data, During early stage kernel start gpio setting changes and screen stops working for a while with strange colors on the screen, and next when the function apalis_t30_gpio_init is run, screen is working properly again.

I think that the problem is LVDS transceiver GPIO configuration (U-Boot vs. early stage booting Linux kernel)

I have attached video how it looks like.

link text

And dmesg output up to the screen display working properly:

dmesg
[    0.000000] Linux version 3.1.10-ge8678dd-dirty (root@kamil-VirtualBox) (gcc version 5.2.1 20151005 (Linaro GCC 5.2-2015.11-2) ) #7 SMP PREEMPT Wed Apr 26 12:54:05 CEST 2017
[    0.000000] CPU: ARMv7 Processor [412fc099] revision 9 (ARMv7), cr=10c5387d
[    0.000000] CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: Toradex Apalis T30
[    0.000000] Found fbmem: 00c00000@ff300000
[    0.000000] Tegra reserved memory:
[    0.000000] LP0:                     00000000 - 00000000
[    0.000000] Bootloader framebuffer:  ff300000 - ffefffff
[    0.000000] Bootloader framebuffer2: 00000000 - 00000000
[    0.000000] Framebuffer:             fe600000 - feefffff
[    0.000000] 2nd Framebuffer:         fef00000 - ffefffff
[    0.000000] Carveout:                00000000 - 00000000
[    0.000000] Vpr:                     00000000 - 00000000
[    0.000000] Memory policy: ECC disabled, Data cache writealloc
[    0.000000] On node 0 totalpages: 517376
[    0.000000] free_area_init_node: node 0, pgdat c0951740, node_mem_map c0a09000
[    0.000000]   Normal zone: 1440 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 162400 pages, LIFO batch:31
[    0.000000]   HighMem zone: 3139 pages used for memmap
[    0.000000]   HighMem zone: 350397 pages, LIFO batch:31
[    0.000000] fuse_speedo_calib: ATE prog ver 4.0
[    0.000000] Tegra3: CPU Speedo ID 2, Soc Speedo ID 2
[    0.000000] Tegra Revision: A03 SKU: 0xb1 CPU Process: 2 Core Process: 0
[    0.000000] tegra: PLLP fixed rate: 408000000
[    0.000000] Lowering sbus maximum rate from 378000000 to 334000000
[    0.000000] Lowering vde maximum rate from 600000000 to 520000000
[    0.000000] Lowering mpe maximum rate from 600000000 to 520000000
[    0.000000] Lowering 2d maximum rate from 600000000 to 520000000
[    0.000000] Lowering epp maximum rate from 600000000 to 520000000
[    0.000000] Lowering 3d maximum rate from 600000000 to 520000000
[    0.000000] Lowering 3d2 maximum rate from 600000000 to 520000000
[    0.000000] Lowering se maximum rate from 625000000 to 520000000
[    0.000000] Lowering host1x maximum rate from 300000000 to 267000000
[    0.000000] Lowering cbus maximum rate from 700000000 to 520000000
[    0.000000] Lowering pll_c maximum rate from 1400000000 to 1066000000
[    0.000000] Lowering ndflash maximum rate from 240000000 to 200000000
[    0.000000] Lowering sbc1 maximum rate from 160000000 to 100000000
[    0.000000] Lowering sbc2 maximum rate from 160000000 to 100000000
[    0.000000] Lowering sbc3 maximum rate from 160000000 to 100000000
[    0.000000] Lowering sbc4 maximum rate from 160000000 to 100000000
[    0.000000] Lowering sbc5 maximum rate from 160000000 to 100000000
[    0.000000] Lowering sbc6 maximum rate from 160000000 to 100000000
[    0.000000] Lowering dsia maximum rate from 500000000 to 432500000
[    0.000000] Lowering dsib maximum rate from 500000000 to 432500000
[    0.000000] Lowering cpu_g maximum rate from 1700000000 to 1400000000
[    0.000000] tegra3_dvfs: cold offset 50000000 is too high for regular dvfs limit 1000000
[    0.000000] tegra3_dvfs: cold offset 50000000 is too high for regular dvfs limit 1000000
[    0.000000] tegra3_dvfs: cold offset 50000000 is too high for regular dvfs limit 1000000
[    0.000000] tegra3_dvfs: cold offset 50000000 is too high for regular dvfs limit 1000000
[    0.000000] tegra dvfs: VDD_CPU nominal 1125mV, scaling enabled
[    0.000000] tegra dvfs: VDD_CORE nominal 1300mV, scaling enabled
[    0.000000] L310 cache controller enabled
[    0.000000] l2x0: 8 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x7e080001, Cache size: 1048576 B
[    0.000000] PERCPU: Embedded 8 pages/cpu @c1bfd000 s10336 r8192 d14240 u32768
[    0.000000] pcpu-alloc: s10336 r8192 d14240 u32768 alloc=8*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 512797
[    0.000000] Kernel command line: core_edp_mv=1300 usb_high_speed=1 ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 rootwait igb_mac=00:14:2d:29:3a:e7 consoleblank=0 no_console_suspend=1 console=tty1 console=ttyS0,115200n8 debug_uartport=lsport,0 vmalloc=256M mem=2035M@2048M fbmem=12M@4083M video=tegrafb0:1024x768-16@60 fbcon=map:0
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 2021MB = 2021MB total
[    0.000000] Memory: 2039908k/2039908k available, 43932k reserved, 1414144K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     DMA     : 0xff000000 - 0xffe00000   (  14 MB)
[    0.000000]     vmalloc : 0xe8800000 - 0xf8000000   ( 248 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe8000000   ( 640 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc086dd2c   (8600 kB)
[    0.000000]       .init : 0xc086e000 - 0xc08c3860   ( 343 kB)
[    0.000000]       .data : 0xc08c4000 - 0xc09540b4   ( 577 kB)
[    0.000000]        .bss : 0xc09540d8 - 0xc09cd530   ( 486 kB)
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000] NR_IRQS:800
[    0.000000] sched_clock: 32 bits at 1000kHz, resolution 1000ns, wraps every 4294967ms
[    0.000000] Console: colour dummy device 80x30
[    0.000000] console [tty1] enabled
[    0.003060] Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
[    0.090130] pid_max: default: 32768 minimum: 301
[    0.090500] Mount-cache hash table entries: 512
[    0.091688] Initializing cgroup subsys blkio
[    0.091833] CPU: Testing write buffer coherency: ok
[    0.091935] ftrace: allocating 23737 entries in 70 pages
[    0.124419] Brought up 4 CPUs
[    0.124466] SMP: Total of 4 processors activated (4787.40 BogoMIPS).
[    0.125604] devtmpfs: initialized
[    0.130969] print_constraints: dummy: 
[    0.131407] NET: Registered protocol family 16
[    0.132717] host1x bus init
[    0.132946] Serial: 8250/16550 driver, 9 ports, IRQ sharing disabled
[    0.406952] apalis_t30_edp_init: CPU regulator 6000 mA
[    0.407045] Selecting UARTA as the debug console
[    0.407089] The debug console clock name is uarta_dbg
[    0.407453] serial8250.0: ttyS0 at MMIO 0x70006000 (irq = 68) is a Tegra
[    0.945421] console [ttyS0] enabled
[    0.973288] Registering the device TPS62360
[    0.978050] Clear bootloader IO dpd settings
[    1.063596] tegra: invalid EMC DFS table: entry for max rate 800000 kHz is not found
[    1.074223] tegra_iovmm_register: added iovmm-smmu
[    1.090604] bio: create slab <bio-0> at 0
[    1.095550] i2c-core: driver [tps6591x] using legacy suspend method
[    1.101865] i2c-core: driver [tps6591x] using legacy resume method
[    1.108543] SCSI subsystem initialized
[    1.112559] libata version 3.00 loaded.
[    1.115315] usbcore: registered new interface driver usbfs
[    1.120941] usbcore: registered new interface driver hub
[    1.126420] usbcore: registered new device driver usb
[    1.131644] tegra-otg tegra-otg: otg transceiver registered
[    1.139017] stmpe 4-0041: stmpe811 detected, chip id: 0x811
[    1.145917] tps6591x 4-002d: VERNUM is 02
[    1.152326] print_constraints: tps6591x_VDD_1: 1350 mV normal standby
[    1.160621] print_constraints: tps6591x_VDD_2: 1050 mV normal standby
[    1.168587] print_constraints: tps6591x_VDDCTRL: 800 <--> 1300 mV at 1012 mV normal standby
[    1.177650] print_constraints: tps6591x_VIO: 1800 mV normal standby
[    1.185223] print_constraints: tps6591x_LDO_1: 1800 mV normal standby
[    1.191730] set_supply: tps6591x_LDO_1: supplied by tps6591x_VIO
[    1.198953] print_constraints: tps6591x_LDO_2: 1200 mV normal standby
[    1.205458] set_supply: tps6591x_LDO_2: supplied by tps6591x_VIO
[    1.212043] print_constraints: tps6591x_LDO_3: 1200 mV normal standby
[    1.219188] print_constraints: tps6591x_LDO_4: 1000 <--> 1400 mV at 1200 mV normal standby
[    1.228008] print_constraints: tps6591x_LDO_5: 2800 mV normal standby
[    1.235033] print_constraints: tps6591x_LDO_6: 1000 <--> 1100 mV at 1100 mV normal standby
[    1.243372] set_supply: tps6591x_LDO_6: supplied by tps6591x_VIO
[    1.250673] print_constraints: tps6591x_LDO_7: 1200 mV normal standby
[    1.257181] set_supply: tps6591x_LDO_7: supplied by tps6591x_VIO
[    1.264262] print_constraints: tps6591x_LDO_8: 1000 mV normal standby
[    1.270751] set_supply: tps6591x_LDO_8: supplied by tps6591x_VIO
[    1.279586] print_constraints: tps62360: 900 <--> 1400 mV at 1230 mV normal standby
[    1.287570] pps_core: LinuxPPS API ver. 1 registered
[    1.292576] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.301785] PTP clock support registered
[    1.306063] Advanced Linux Sound Architecture Driver Version 1.0.24.
[    1.313088] Bluetooth: Core ver 2.16
[    1.316740] NET: Registered protocol family 31
[    1.321224] Bluetooth: HCI device and connection manager initialized
[    1.327602] Bluetooth: HCI socket layer initialized
[    1.332509] Bluetooth: L2CAP socket layer initialized
[    1.337621] Bluetooth: SCO socket layer initialized
[    1.343368] print_constraints: fixed_reg_en_hdmi: 1800 mV normal 
[    1.349792] print_constraints: fixed_reg_v3_3: 3300 mV normal 
[    1.356107] print_constraints: gpio_reg_sdmmc3_vdd_sel: 1800 <--> 3300 mV at 1800 mV normal standby
[    1.365227] set_supply: gpio_reg_sdmmc3_vdd_sel: supplied by fixed_reg_v3_3
[    1.373095] tegra: failed to map regulator to power detect cell pwrdet_sdmmc3(-19)
[    1.380788] tegra: failed regulators mapping - io power detection is left always on
[    1.388496] Switching to clocksource timer_us
[    1.393521] Switched to NOHz mode on CPU #2
[    1.394316] Switched to NOHz mode on CPU #3
[    1.401067] Switched to NOHz mode on CPU #0
[    1.402677] Switched to NOHz mode on CPU #1
[    1.408315] nvmap_page_pool_init: nvmap uc page pool size=63747 pages
[    1.481171] nvmap_page_pool_init: nvmap pool = uc, highmem=63747, pool_size=63747,totalram=509977, freeram=445276, totalhigh=353536, freehigh=289645
[    1.784693] nvmap_page_pool_init: nvmap wc page pool size=63747 pages
[    1.857534] nvmap_page_pool_init: nvmap pool = wc, highmem=63747, pool_size=63747,totalram=509977, freeram=381416, totalhigh=353536, freehigh=225785
[    2.159521] nvmap_page_pool_init: nvmap iwb page pool size=63747 pages
[    2.232467] nvmap_page_pool_init: nvmap pool = iwb, highmem=63747, pool_size=63747,totalram=509977, freeram=317525, totalhigh=353536, freehigh=161894
[    2.536177] tegra-nvmap tegra-nvmap: created carveout iram (255KiB)
[    2.557087] NET: Registered protocol family 2
[    2.561724] IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
[    2.569512] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
[    2.579474] TCP bind hash table entries: 65536 (order: 7, 786432 bytes)
[    2.587941] TCP: Hash tables configured (established 131072 bind 65536)
[    2.594596] TCP reno registered
[    2.597761] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    2.603759] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    2.610526] NET: Registered protocol family 1
[    2.615393] RPC: Registered named UNIX socket transport module.
[    2.621338] RPC: Registered udp transport module.
[    2.626088] RPC: Registered tcp transport module.
[    2.630809] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    2.637292] PCI: CLS 0 bytes, default 32
[    2.640087] host1x host1x: initialized
[    2.644010] PMU: registered new PMU device of type 0
[    2.649511] Tegra auto-hotplug initialized: disabled
[    2.654539] cpu-tegra: init EDP limit: 1250 MHz
[    2.659833] PCIE.C: tegra_pcie_enable_regulators : regulator hvdd_pex
[    2.666411] PCIE.C: tegra_pcie_enable_regulators : regulator pexio
[    2.672630] tegra_pcie_enable_regulators: unable to get pexio regulator
[    2.679289] PCIE.C: tegra_pcie_enable_regulators : regulator avdd_plle
[    2.887875] PCIE: port 0: link down, retrying
[    3.092545] PCIE: port 0: link down, retrying
[    3.297273] PCIE: port 0: link down, retrying
[    3.301630] PCIE: port 0: link down, ignoring
[    3.306115] pci 0000:00:00.0: [10de:0e1d] type 1 class 0x000604
[    3.306179] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    3.306191] pci 0000:00:00.0: PME# disabled
[    3.306229] PCI: bus0: Fast back to back transfers disabled
[    3.311875] pci 0000:01:00.0: [8086:08b1] type 0 class 0x000280
[    3.311926] pci 0000:01:00.0: reg 10: [mem 0x00000000-0x00001fff 64bit]
[    3.312102] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[    3.312115] pci 0000:01:00.0: PME# disabled
[    3.322969] PCI: bus1: Fast back to back transfers disabled
[    3.328865] pci 0000:02:00.0: [10de:0e1d] type 1 class 0x000604
[    3.328921] pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    3.328931] pci 0000:02:00.0: PME# disabled
[    3.328966] PCI: bus2: Fast back to back transfers disabled
[    3.334623] pci 0000:03:00.0: [8086:157b] type 0 class 0x000200
[    3.334657] pci 0000:03:00.0: reg 10: [mem 0x00000000-0x0001ffff]
[    3.334694] pci 0000:03:00.0: reg 18: [io  0x0000-0x001f]
[    3.334715] pci 0000:03:00.0: reg 1c: [mem 0x00000000-0x00003fff]
[    3.334840] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold
[    3.334852] pci 0000:03:00.0: PME# disabled
[    3.352960] PCI: bus3: Fast back to back transfers disabled
[    3.358810] pci 0000:02:00.0: BAR 8: assigned [mem 0x10000000-0x100fffff]
[    3.365620] pci 0000:02:00.0: BAR 7: assigned [io  0x10000000-0x10000fff]
[    3.372413] pci 0000:03:00.0: BAR 0: assigned [mem 0x10000000-0x1001ffff]
[    3.379220] pci 0000:03:00.0: BAR 0: set to [mem 0x10000000-0x1001ffff] (PCI address [0x10000000-0x1001ffff])
[    3.389147] pci 0000:03:00.0: BAR 3: assigned [mem 0x10020000-0x10023fff]
[    3.396011] pci 0000:03:00.0: BAR 3: set to [mem 0x10020000-0x10023fff] (PCI address [0x10020000-0x10023fff])
[    3.405945] pci 0000:03:00.0: BAR 2: assigned [io  0x10000000-0x1000001f]
[    3.412742] pci 0000:03:00.0: BAR 2: set to [io  0x10000000-0x1000001f] (PCI address [0x10000000-0x1000001f])
[    3.422670] pci 0000:02:00.0: PCI bridge to [bus 03-03]
[    3.427907] pci 0000:02:00.0:   bridge window [io  0x10000000-0x10000fff]
[    3.434706] pci 0000:02:00.0:   bridge window [mem 0x10000000-0x100fffff]
[    3.441511] pci 0000:00:00.0: BAR 8: assigned [mem 0x10100000-0x101fffff]
[    3.448314] pci 0000:01:00.0: BAR 0: assigned [mem 0x10100000-0x10101fff 64bit]
[    3.455646] pci 0000:01:00.0: BAR 0: set to [mem 0x10100000-0x10101fff 64bit] (PCI address [0x10100000-0x10101fff])
[    3.466093] pci 0000:00:00.0: PCI bridge to [bus 01-01]
[    3.471320] pci 0000:00:00.0:   bridge window [mem 0x10100000-0x101fffff]
[    3.509117] highmem bounce pool size: 64 pages
[    3.514369] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    3.521339] fuse init (API version 7.17)
[    3.525599] msgmni has been set to 1222
[    3.530293] io scheduler noop registered (default)
[    3.537050] mpe mpe: initialized
[    3.542529] gr3d gr3d: initialized
[    3.548124] gr2d gr2d: initialized
[    3.552019] isp isp: initialized
[    3.555789] tegradc tegradc.0: probed
[    3.559579] tegradc tegradc.0: use cmd options for tegrafb0: 1024x768-16@60
[    3.566602] tegradc tegradc.0: switching framebuffer to 1024x768
[    3.572610] tegradc tegradc.0: Calculated sync href=0 vref=1
[    3.578280] tegradc tegradc.0: using mode 1024x768 pclk=65002000 href=0 vref=1
[    3.590173] tegradc tegradc.0: switching framebuffer to 1024x768
[    3.590182] tegradc tegradc.0: Calculated sync href=0 vref=1
[    3.590191] tegradc tegradc.0: using mode 1024x768 pclk=65002000 href=0 vref=1
[    3.614596] Console: switching to colour frame buffer device 128x48
[    3.656540] tegradc tegradc.0: probed
[    3.677383] tegradc tegradc.1: probed
[    3.681344] tegradc tegradc.1: use default mode for tegrafb1: 640x480-16@60
[    3.688390] tegradc tegradc.1: Unusuall display aspect ratio.                 You may encounter problems with base resolution
[    3.700295] tegradc tegradc.1: Unusuall display aspect ratio.                 You may encounter problems with base resolution
[    3.711724] tegradc tegradc.1: Unusuall display aspect ratio.                 You may encounter problems with base resolution
[    3.723150] tegradc tegradc.1: switching framebuffer to 640x480
[    3.729129] tegradc tegradc.1: using mode 640x480 pclk=23750000 href=1 vref=1
[    3.741569] tegradc tegradc.1: hdmi: can't set audio to 44100 at 23750000 pix_clock
[    3.749366] tegradc tegradc.1: probed
[    3.803866] tegra_uart.3: ttyHS3 at MMIO 0x70006300 (irq = 122) is a TEGRA_UART
[    3.932939] Registered UART port ttyHS3
[    3.938684] tegra_uart.1: ttyHS1 at MMIO 0x70006040 (irq = 69) is a TEGRA_UART
[    4.092961] Registered UART port ttyHS1
[    4.100570] tegra_uart.2: ttyHS2 at MMIO 0x70006200 (irq = 78) is a TEGRA_UART
[    4.252954] Registered UART port ttyHS2
[    4.260715] Initialized tegra uart driver
[    4.273469] loop: module loaded
[    4.281030] tegra-sata tegra-sata.0: version 1.0
[    4.281074] create_regulator: tps6591x_LDO_6: Failed to create debugfs directory
[    4.293276] tegra-sata tegra-sata.0: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl TEGRA-SATA mode
[    4.306418] tegra-sata tegra-sata.0: flags: 64bit ncq sntf pm led pio slum part apst 
[    4.319171] scsi0 : tegra-sata
[    4.326520] ata1: SATA max UDMA/133 irq 55
[    4.335294] Intel(R) Gigabit Ethernet Network Driver - version 5.2.17

During boot kernel will reset a lot of peripheral setting before setting them again (like clocks, gpios, display subsystem etc.). if you really need a display in u-boot the easiest solution would be to blank the screen or disable the backlight before jumping to kernel from u-boot and allowing kernel to enable everything when it’s ready. You can also not enable the display in u-boot and just wait for kernel to do it. Alternatively you can have an look in kernel init functions for peripherals and debug it there.
Instead of adding code to apalis_t30_gpio_init just adjust static struct gpio apalis_t30_gpios[] located in the same file.

Already changed to:

        {LVDS_MODE,             GPIOF_OUT_INIT_HIGH,            "LVDS: Single/Dual Ch"},
        {LVDS_6B_8B_N,          GPIOF_OUT_INIT_LOW,             "LVDS: 18/24 Bit Mode"},
        {LVDS_OE,               GPIOF_OUT_INIT_HIGH,            "LVDS: Output Enable"},
        {LVDS_PDWN_N,           GPIOF_OUT_INIT_HIGH,            "LVDS: Power Down"},
        {LVDS_R_F_N,            GPIOF_OUT_INIT_HIGH,            "LVDS: Clock Polarity"},
        {LVDS_MAP,              GPIOF_OUT_INIT_LOW,             "LVDS: Colour Mapping"},
        {LVDS_RS,               GPIOF_OUT_INIT_HIGH,            "LVDS: Swing Mode"},
        {LVDS_DDR_N,            GPIOF_OUT_INIT_HIGH,            "LVDS: DDRclk Disable"},

but no success. Looks like need to disable lvds screen during boot.