100rabh
September 26, 2019, 10:50am
1
I want to set some pins high and some pins to low during boot time. At normal/ideal operation device is working fine but at the boot time ( during kernel boot ) some unexpected behaviour is seen. U-boot is also working as configured. So i tried to modify the dts file in linux kernel (arch/arm/boot/dts/vf-colibri.dtsi ). I tried two methods using gpios and pinctrl-assert-gpio (commented for now).
Following is the diff
@@ -171,10 +171,29 @@
&usbphy1 {
status = "okay";
};
+&gpio0 {
+ gpios = <5 GPIO_ACTIVE_LOW>;
+};
+&gpio1 {
+ gpios = <19 GPIO_ACTIVE_HIGH>;
+};
+&gpio2 {
+ gpios = <2 GPIO_ACTIVE_LOW>,
+ <0 GPIO_ACTIVE_HIGH>;
+};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_0 &pinctrl_hog_1>;
+ /* pinctrl-assert-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>,
+ <&gpio1 31 GPIO_ACTIVE_LOW>,
+ <&gpio2 2 GPIO_ACTIVE_LOW>,
+ <&gpio2 28 GPIO_ACTIVE_LOW>,
+ <&gpio2 0 GPIO_ACTIVE_HIGH>,
+ <&gpio3 27 GPIO_ACTIVE_HIGH>; */
vf610-colibri {
pinctrl_flexcan0: can0grp {
@@ -191,7 +210,7 @@
>;
};
- pinctrl_dcu0_1: dcu0grp_1 {
+/* pinctrl_dcu0_1: dcu0grp_1 {
fsl,pins = <
VF610_PAD_PTE0__DCU0_HSYNC 0x1902
VF610_PAD_PTE1__DCU0_VSYNC 0x1902
@@ -223,7 +242,7 @@
VF610_PAD_PTE28__DCU0_B7 0x1902
>;
};
-
+*/
pinctrl_dspi1: dspi1grp {
fsl,pins = <
VF610_PAD_PTD5__DSPI1_CS0 0x33e2
@@ -268,49 +287,87 @@
pinctrl_hog_0: hoggrp-0 {
fsl,pins = <
- VF610_PAD_PTA12__GPIO_5 0x22ed
- VF610_PAD_PTA17__GPIO_7 0x22ed
VF610_PAD_PTA20__GPIO_10 0x22ed
- VF610_PAD_PTA21__GPIO_11 0x22ed
VF610_PAD_PTA30__GPIO_20 0x22ed
VF610_PAD_PTA31__GPIO_21 0x22ed
- VF610_PAD_PTB6__GPIO_28 0x22ed
VF610_PAD_PTB7__GPIO_29 0x22ed
- VF610_PAD_PTB16__GPIO_38 0x22ed
VF610_PAD_PTB17__GPIO_39 0x22ed
- VF610_PAD_PTB18__GPIO_40 0x22ed
VF610_PAD_PTB21__GPIO_43 0x22ed
VF610_PAD_PTB22__GPIO_44 0x22ed
- VF610_PAD_PTC1__GPIO_46 0x22ed
VF610_PAD_PTC2__GPIO_47 0x22ed
VF610_PAD_PTC3__GPIO_48 0x22ed
VF610_PAD_PTC4__GPIO_49 0x22ed
VF610_PAD_PTC5__GPIO_50 0x22ed
- VF610_PAD_PTC6__GPIO_51 0x22ed
- VF610_PAD_PTC7__GPIO_52 0x22ed
VF610_PAD_PTC8__GPIO_53 0x22ed
- VF610_PAD_PTD30__GPIO_64 0x22ed
VF610_PAD_PTD29__GPIO_65 0x22ed
- VF610_PAD_PTD28__GPIO_66 0x22ed
VF610_PAD_PTD26__GPIO_68 0x22ed
- VF610_PAD_PTD25__GPIO_69 0x22ed
VF610_PAD_PTD24__GPIO_70 0x22ed
- VF610_PAD_PTD9__GPIO_88 0x22ed
VF610_PAD_PTD10__GPIO_89 0x22ed
VF610_PAD_PTD11__GPIO_90 0x22ed
VF610_PAD_PTD12__GPIO_91 0x22ed
- VF610_PAD_PTD13__GPIO_92 0x22ed
VF610_PAD_PTB26__GPIO_96 0x22ed
VF610_PAD_PTB28__GPIO_98 0x22ed
VF610_PAD_PTC30__GPIO_103 0x22ed
+ VF610_PAD_PTE0__GPIO_105 0x22ed
+ VF610_PAD_PTE2__GPIO_107 0x22ed
+ VF610_PAD_PTE3__GPIO_108 0x22ed
+ VF610_PAD_PTE20__GPIO_125 0x22ed
+ VF610_PAD_PTE24__GPIO_129 0x22ed
VF610_PAD_PTA7__GPIO_134 0x22ed
+
+ VF610_PAD_PTB16__GPIO_38 0x22ed
+ VF610_PAD_PTB18__GPIO_40 0x22ed
+ VF610_PAD_PTC6__GPIO_51 0x22ed
+ VF610_PAD_PTD30__GPIO_64 0x22ed
+ VF610_PAD_PTE18__GPIO_123 0x22ed
+
+ VF610_PAD_PTA17__GPIO_7 0x22ed
+ VF610_PAD_PTE16__GPIO_121 0x22ed
+ VF610_PAD_PTE21__GPIO_126 0x22ed
+ VF610_PAD_PTE22__GPIO_127 0x22ed
+
+ VF610_PAD_PTD25__GPIO_69 0x22ed
+ VF610_PAD_PTE5__GPIO_110 0x22ed
+ VF610_PAD_PTE6__GPIO_111 0x22ed
+ VF610_PAD_PTE7__GPIO_112 0x22ed
+
+ VF610_PAD_PTA12__GPIO_5 0x22ed
+ VF610_PAD_PTD31__GPIO_63 0x22ed
+ VF610_PAD_PTD28__GPIO_66 0x22ed
+ VF610_PAD_PTD13__GPIO_92 0x22ed
+
+ VF610_PAD_PTC1__GPIO_46 0x22ed
+ VF610_PAD_PTD9__GPIO_88 0x22ed
+
+ VF610_PAD_PTB6__GPIO_28 0x22ed
+ VF610_PAD_PTC7__GPIO_52 0x22ed
+ VF610_PAD_PTE1__GPIO_106 0x22ed
+ VF610_PAD_PTE8__GPIO_113 0x22ed
+ VF610_PAD_PTE9__GPIO_114 0x22ed
+ VF610_PAD_PTE10__GPIO_115 0x22ed
+ VF610_PAD_PTE11__GPIO_116 0x22ed
+ VF610_PAD_PTE12__GPIO_117 0x22ed
+ VF610_PAD_PTE13__GPIO_118 0x22ed
+ VF610_PAD_PTE14__GPIO_119 0x22ed
+ VF610_PAD_PTE15__GPIO_120 0x22ed
+ VF610_PAD_PTE17__GPIO_122 0x22ed
+ VF610_PAD_PTE19__GPIO_124 0x22ed
+ VF610_PAD_PTE23__GPIO_128 0x22ed
+ VF610_PAD_PTE25__GPIO_130 0x22ed
+ VF610_PAD_PTE26__GPIO_131 0x22ed
+ VF610_PAD_PTE27__GPIO_132 0x22ed
+ VF610_PAD_PTE28__GPIO_133 0x22ed
+
+ VF610_PAD_PTE4__GPIO_109 0x22ed
+
+ VF610_PAD_PTA21__GPIO_11 0x22ed
>;
};
Please let me if any thing else required.
100rabh
September 26, 2019, 12:03pm
2
file in proper format
&gpio0 {
gpios = < 5 GPIO_ACTIVE_LOW >;
};
&gpio1 {
gpios = < 19 GPIO_ACTIVE_HIGH >;
};
&gpio2 {
gpios = < 2 GPIO_ACTIVE_LOW > ,
< 0 GPIO_ACTIVE_HIGH > ;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = < &pinctrl_hog_0 &pinctrl_hog_1 >;
pinctrl-assert-gpios = < &gpio0 5 GPIO_ACTIVE_LOW >,
< &gpio1 31 GPIO_ACTIVE_LOW >,
< &gpio2 2 GPIO_ACTIVE_LOW >,
< &gpio2 28 GPIO_ACTIVE_LOW >,
< &gpio2 0 GPIO_ACTIVE_HIGH >,
< &gpio3 27 GPIO_ACTIVE_HIGH > ;
vf610-colibri {
pinctrl_flexcan0: can0grp {
fsl,pins = <
VF610_PAD_PTB14__CAN0_RX 0x31F1
VF610_PAD_PTB15__CAN0_TX 0x31F2
>;
};
:
:
:
pinctrl_hog_0: hoggrp-0 {
fsl,pins = <
VF610_PAD_PTA20__GPIO_10 0x22ed
VF610_PAD_PTA30__GPIO_20 0x22ed
VF610_PAD_PTA31__GPIO_21 0x22ed
VF610_PAD_PTB7__GPIO_29 0x22ed
VF610_PAD_PTB17__GPIO_39 0x22ed
VF610_PAD_PTB21__GPIO_43 0x22ed
VF610_PAD_PTB22__GPIO_44 0x22ed
VF610_PAD_PTC2__GPIO_47 0x22ed
VF610_PAD_PTC3__GPIO_48 0x22ed
VF610_PAD_PTC4__GPIO_49 0x22ed
VF610_PAD_PTC5__GPIO_50 0x22ed
VF610_PAD_PTC8__GPIO_53 0x22ed
VF610_PAD_PTD29__GPIO_65 0x22ed
VF610_PAD_PTD26__GPIO_68 0x22ed
VF610_PAD_PTD24__GPIO_70 0x22ed
VF610_PAD_PTD10__GPIO_89 0x22ed
VF610_PAD_PTD11__GPIO_90 0x22ed
VF610_PAD_PTD12__GPIO_91 0x22ed
VF610_PAD_PTB26__GPIO_96 0x22ed
VF610_PAD_PTB28__GPIO_98 0x22ed
VF610_PAD_PTC30__GPIO_103 0x22ed
VF610_PAD_PTE0__GPIO_105 0x22ed
VF610_PAD_PTE2__GPIO_107 0x22ed
VF610_PAD_PTE3__GPIO_108 0x22ed
VF610_PAD_PTE20__GPIO_125 0x22ed
VF610_PAD_PTE24__GPIO_129 0x22ed
VF610_PAD_PTA7__GPIO_134 0x22ed
VF610_PAD_PTB16__GPIO_38 0x22ed
VF610_PAD_PTB18__GPIO_40 0x22ed
VF610_PAD_PTC6__GPIO_51 0x22ed
VF610_PAD_PTD30__GPIO_64 0x22ed
VF610_PAD_PTE18__GPIO_123 0x22ed
VF610_PAD_PTA17__GPIO_7 0x22ed
VF610_PAD_PTE16__GPIO_121 0x22ed
VF610_PAD_PTE21__GPIO_126 0x22ed
VF610_PAD_PTE22__GPIO_127 0x22ed
VF610_PAD_PTD25__GPIO_69 0x22ed
VF610_PAD_PTE5__GPIO_110 0x22ed
VF610_PAD_PTE6__GPIO_111 0x22ed
VF610_PAD_PTE7__GPIO_112 0x22ed
VF610_PAD_PTA12__GPIO_5 0x22ed
VF610_PAD_PTD31__GPIO_63 0x22ed
VF610_PAD_PTD28__GPIO_66 0x22ed
VF610_PAD_PTD13__GPIO_92 0x22ed
VF610_PAD_PTC1__GPIO_46 0x22ed
VF610_PAD_PTD9__GPIO_88 0x22ed
VF610_PAD_PTB6__GPIO_28 0x22ed
VF610_PAD_PTC7__GPIO_52 0x22ed
VF610_PAD_PTE1__GPIO_106 0x22ed
VF610_PAD_PTE8__GPIO_113 0x22ed
VF610_PAD_PTE9__GPIO_114 0x22ed
VF610_PAD_PTE10__GPIO_115 0x22ed
VF610_PAD_PTE11__GPIO_116 0x22ed
VF610_PAD_PTE12__GPIO_117 0x22ed
VF610_PAD_PTE13__GPIO_118 0x22ed
VF610_PAD_PTE14__GPIO_119 0x22ed
VF610_PAD_PTE15__GPIO_120 0x22ed
VF610_PAD_PTE17__GPIO_122 0x22ed
VF610_PAD_PTE19__GPIO_124 0x22ed
VF610_PAD_PTE23__GPIO_128 0x22ed
VF610_PAD_PTE25__GPIO_130 0x22ed
VF610_PAD_PTE26__GPIO_131 0x22ed
VF610_PAD_PTE27__GPIO_132 0x22ed
VF610_PAD_PTE28__GPIO_133 0x22ed
VF610_PAD_PTE4__GPIO_109 0x22ed
VF610_PAD_PTA21__GPIO_11 0x22ed
>;
};
:
:
};
Hi @ryan
Could you provide the version of the Hardware (including carrier board) and Software of your module?
At normal/ideal operation device is working fine but at the boot time ( during kernel boot ) some unexpected behaviour is seen.
What exactly is not working? What is your application?
Which SODIMM Pins do you want to set high/low?
Best regards,
100rabh
September 27, 2019, 8:18am
4
SODIMM PIN number
100rabh
September 27, 2019, 8:06am
5
Module : colibri vf 50
Customized carrier board in accordance to iris
image version : customized on base of Colibri -VF_Console-Image 2.7b5
I want to set low the following pins
<&gpio1 31 GPIO_ACTIVE_LOW >,
For doing that I had done up metioned configuration in dts and tried two mentioned method i.e. gpios and pinctrl-assert-gpio (one by one). Apart from it i tried to use (no-init-on-reset) but without any luck. At boot time in uboot the pin value are low but after that when kernel comes up the pin resets to high. Everything is working fine in device once application gets the control and export it in user space. I am struggling with these two following queries.
Am I defining the gpios/pinctrl-assert-gpio at the right location/node or file (currently modifying
If not then what is the right method to make these particular pins low in dts so that when control switches from uboot to kernel the pins state do not change.
Best regards,
Ryan
Hi @ryan
You can neither set the value nor the direction in the device tree for the Pins. In the device-tree you can do the correct muxing of the SOC Pins to define their Functionality.
If you want to have GPIO set at Boot time, then first Instance is to set them in U-Boot. Further once the Linux kernel takes over, then you would need a driver which handles the GPIOs.
For the specific pins, these pins are defined as Pull-Up in the Devicetree, you can set them as Pull-Down as explained here .
Best regards,
100rabh
September 28, 2019, 6:13am
7
hi @jaski.tx
gpios = <&gpio1 31 GPIO_ACTIVE_LOW >;
Best regards,
Perfect that it worked.
Regarding the Property GPIO_ACTIVE_LOOK it describes the polarity of the Pin as explained here .
Best regards,
Hello,
i found this GPIO handling in uboot where it says the pins should be set via
# setenv set-io 'gpio set <gpio-number>'
# setenv bootcmd 'run set-io; run ubiboot; run sdboot'
# saveenv
but i am not sure how to even make sure the Uboot command is active as my SSH is always disconnecting. And i do not know what tool to use to read the usb for the uboot info when debugging it.
Hi @busssard ,
You can get access to u-boot by connecting with UART_A.quickstart guide for setting up the same
