Sclk glitching on lpspi1 on apalis imx8

Technical Support
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1

Hi,

I am trying to setup lpspi1 on Apalis iMX8. I get glitches on the SCLK depending on what I connect. These glitches seem to be read as extra clock pulses on the spi so all readings are wrong.

I am evaluating on the Apalis Evaluation board , and have tried both with the 1nF on C104 mounted and not mounted.

This is my device tree setup:

&dma_subsys {

    lpspi1: spi@5a010000 {
            compatible = "fsl,imx7ulp-spi";
            reg = <0x5a010000 0x10000>;
            #address-cells = <1>;
            #size-cells = <0>;
            interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-parent = <&gic>;
            clocks = <&spi1_lpcg 0>,
                     <&spi1_lpcg 1>;
            clock-names = "per", "ipg";
            assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
            assigned-clock-rates = <60000000>;
            power-domains = <&pd IMX_SC_R_SPI_1>;
            dma-names = "tx","rx";
            dmas = <&edma2 3 0 0>, <&edma2 2 0 1>;
            status = "disabled";
    };

};

           pinctrl_lpspi1: lpspi1grp {
                    fsl,pins = <
                            IMX8QM_ADC_IN3_DMA_SPI1_SCK                     0x0600004c
                            IMX8QM_ADC_IN4_DMA_SPI1_SDO                     0x0600004c
                            IMX8QM_ADC_IN5_DMA_SPI1_SDI                     0x0600004c
                            IMX8QM_ADC_IN6_LSIO_GPIO3_IO24                  0x0600004c
                            IMX8QM_ADC_IN7_LSIO_GPIO3_IO25                  0x0600004c
                    >;
            };

&lpspi1 {
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_lpspi1>;
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>, <&lsio_gpio3 25 GPIO_ACTIVE_LOW>;
status = “okay”;

    spidev2_cs0: spi@0 {
            compatible = "toradex,evalspi";
            reg = <0>;
            spi-max-frequency = <4000000>;
    };

    spidev2_cs1: spi@1 {
            compatible = "toradex,evalspi";
            reg = <1>;
            spi-max-frequency = <4000000>;
    };

};

This output of tdx-info:

Software summary
------------------------------------------------------------
Bootloader:               U-Boot
Kernel version:           5.4.193-5.7.0-devel+git.f78299297185 #1-TorizonCore SMP PREEMPT Thu May 11 08:53:23 UTC 2023
Kernel command line:      pci=nomsi root=LABEL=otaroot rootfstype=ext4 quiet logo.nologo vt.global_cursor_default=0 plymouth.ignore-serial-consoles splash ostree=/ostree/boot.1/torizon/0dce0ef4758c070a8509d9b6fcbb83136214e2d045a7f3b7669cc8266b40852b/0
Distro name:              NAME="Custom TorizonCore Variant"
Distro version:           VERSION_ID=5.7.0-devel-20230511085225-build.0
Hostname:                 apalis-imx8-07278529
------------------------------------------------------------

Hardware info
------------------------------------------------------------
HW model:                 Toradex Apalis iMX8QM V1.1 on Custom Carrier Board
Toradex version:          0037 V1.1E
Serial number:            07278529
Processor arch:           aarch64
------------------------------------------------------------

Is there some known issue with glitches on lpspi1 SCLK?
Anything else I should look for or think of?

2

Could you please provides details about the glitches you are observing? Do you have an oscilogram?

3

The glitches appear when there is a slave attached to the spi-bus.

I have tried with both our custom carrier board, and as in this case with the Apalis Evaluation Board.

Here is the test setup:

  • Apalis Evaluation Board V1.1C
  • Apalis IMX8QM 4GB WB IT
  • TotalPhase Promira connected to Apalis Evaluation Board X16 pins 2 (CS), 4(MISO), 5(MOSI), 6 (SCLK)
  • RIGOL MS5104 Oscilloscope connected to SCLK
  • Saleae Logic Pro 8 connected to CS, MOSI, SCLK (MISO was left out during this measurement).

From the Oscilloscope:

LPSPI1_glitches
LPSPI1_glitches1024×600 45.6 KB

From the logic analyzer:

LPSPI1_glitches_logic_1
LPSPI1_glitches_logic_11732×975 65.8 KB

Zoomed in on pulse #5:
LPSPI1_glitches_logic_2
LPSPI1_glitches_logic_2541×1096 17.7 KB

From the Control Center/Promira.

LPSPI1_glitches_promira
LPSPI1_glitches_promira1144×247 2.46 KB

4

Hello @jugge,

The ADC inputs voltage range is only 1.8V, not 3.3V as on other Apalis modules. There
are 1k series resistors placed in the ADC lines (not on the touch interface pins) to protect the SoC
input.
When using them as SPI the voltage range is 3.3 volts but the resistors are still present and effect the Clock slope. So try using a lower SPI clock speed, or a different SPI block.

Best Regards,

Matthias