SAI3 on imx6ull with sgtl5000

Hi,

I’m trying to make a devicetree overlay for the sai3 interface on a Colibri imx6ull module (emmc version).
I’ve made the following overlay:

/dts-v1/;
/plugin/;

#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/pinctrl/imx6ul-pinfunc.h>


&{/} {
    compatible = "toradex,colibri-imx6ull-emmc";

    sound {
        compatible = "toradex,colibri-imx6ull-emmc",
                     "simple-audio-card";
        simple-audio-card,name="sgtl5000-audio";
        simple-audio-card,format = "i2s";
        simple-audio-card,bitclock-master = <&dailink_master_cpu>;
        simple-audio-card,frame-master = <&dailink_master_cpu>;
        simple-audio-card,widgets =
                "Microphone", "Mic Jack",
                "Line", "Line In",
                "Line", "Line Out",
                "Headphone", "Headphone Jack";
        simple-audio-card,routing =
                "MIC_IN", "Mick Jack",
                "Mic Jack", "Mic Bias",
                "Headphone Jack", "HP_OUT";

        simple-audio-card,codec {
                sound-dai = <&codec_ext>;
        };

        dailink_master_cpu: simple-audio-card,cpu {
                sound-dai = <&sai3>;
        };

    };
};

&lcdif {
        status="disabled";
};

&backlight {
        status="disabled";
};

&i2c1 {
        codec_ext: sgtl5000@a {
                compatible = "fsl,sgtl5000";
                reg = <0xa>;
                #sound-dai-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_sai3_mclk>;
                clocks = <&clks IMX6UL_CLK_SAI3>;
                clk-names = "mclk";
                VDDA-supply = <&reg_module_3v3_avdd>;
                VDDIO-supply = <&reg_module_3v3>;
                VDDD-supply = <&reg_module_3v3>;
                status="okay";
        };
};

&sai3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai3>;
        assigned-clocks = <&clks IMX6UL_CLK_SAI3_SEL>,
                          <&clks IMX6UL_CLK_SAI3>, <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
        assigned-clock-rates = <2>, <24576000>, <786432000>;
        fsl,sai-asynchronous;
        //fsl,sai-mclk-direction-output;
        status = "okay";
};

&iomuxc {
                pinctrl_sai3: sai3grp {
                        fsl,pins = <
                                MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK      0x1F089
                                MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC      0x17088
                                MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA      0x11088
                                MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA      0x11088
                                MX6UL_PAD_LCD_DATA09__SAI3_MCLK         0x17088
                        >;
                };
                pinctrl_sai3_mclk: sai3grp_mclk {
                        fsl,pins = <
                                MX6UL_PAD_LCD_DATA09__SAI3_MCLK         0x17088
                        >;
                };
};

After boot I get:

Applying Overlay: audio_sgtl5000.dtbo
3281 bytes read in 33 ms (96.7 KiB/s)
8040960 bytes read in 207 ms (37 MiB/s)
8053158 bytes read in 210 ms (36.6 MiB/s)
Kernel image @ 0x81000000 [ 0x000000 - 0x7ab200 ]
## Flattened Device Tree blob at 82100000
   Booting using the fdt blob at 0x82100000
   Loading Ramdisk to 8f851000, end 8ffff1a6 ... OK
   Loading Device Tree to 8f822000, end 8f850fff ... OK
   Updating MTD partitions...

Starting kernel ...

[    0.074375] debugfs: Directory 'dummy-iomuxc-gpr@20e4000' with parent 'regmap' already present!
[    3.411226] fec 20b4000.ethernet: fec clock (0) too fast to get right mii speed
[    4.795515] sgtl5000 0-000a: Error reading chip id -110
Starting version 244.5+

TorizonCore Upstream 5.7.0+build.17 colibri-imx6ull-emmc-07201239 ttymxc0

colibri-imx6ull-emmc-07201239 login:

So for some reason I don’t get a mclk on pin 48 (MX6UL_PAD_LCD_DATA09__SAI3_MCLK).
I’m not sure if the clock configuration is correct. The sgtl5000 needs a MCLK so the Error reading chip error is obvious.

From /sys/kernel/debug/clk/clk_summary I get:

    pll4                              0        0        0   786432000          0     0  50000
       pll4_bypass                    0        0        0   786432000          0     0  50000
          pll4_audio                  0        0        0   786432000          0     0  50000
             pll4_post_div            0        0        0   786432000          0     0  50000
                pll4_audio_div        0        0        0   786432000          0     0  50000
                   sai3_sel           0        0        0   786432000          0     0  50000
                      sai3_pred       0        0        0   393216000          0     0  50000
                         sai3_podf       0        0        0    24576000          0     0  50000
                            sai3       0        0        0    24576000          0     0  50000

Not sure if this is correct? At least to get some clock going on pin 48?

Pinmux settings from /sys/kernel/debug/pinctrl/20e0000.iomuxc/pinmux-pins:

pin 79 (MX6UL_PAD_LCD_DATA09): 2030000.sai (GPIO UNCLAIMED) function iomuxc group sai3grp
pin 80 (MX6UL_PAD_LCD_DATA10): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 81 (MX6UL_PAD_LCD_DATA11): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 82 (MX6UL_PAD_LCD_DATA12): 2030000.sai (GPIO UNCLAIMED) function iomuxc group sai3grp
pin 83 (MX6UL_PAD_LCD_DATA13): 2030000.sai (GPIO UNCLAIMED) function iomuxc group sai3grp
pin 84 (MX6UL_PAD_LCD_DATA14): 2030000.sai (GPIO UNCLAIMED) function iomuxc group sai3grp
pin 85 (MX6UL_PAD_LCD_DATA15): 2030000.sai (GPIO UNCLAIMED) function iomuxc group sai3grp

I also don’t understand why I get this error:

[ 3.408154] fec 20b4000.ethernet: fec clock (0) too fast to get right mii speed

If I remove the overlay this error is also gone. With this error the ethernet interface is not working anymore.

So the question is what’s wrong with this overlay. Any help would really be would be greatly appreciated.

Kind regards,

Chris

Having another look at this… I’ve noticed PLL4 is disabled. How can I enable it?

Regards,

Chris

Hi @sirhc ,

On first look there doesn’t seem to be any obvious mistake on your overlay.

On this solved topic: Device tree configuration for SGTL5000 audio codec someone had a very similar issue with SAI on iMX6ULL with SGTL5000. Can you try the proposed solution and see if it works for you?

Best regards,
Lucas Akira

Hi Lucas,

Thanks for your reply. I’ve seen this post. He was using an external clock as master clock.
The last comment of your colleague was it should also work with an internal clock, but unfortunately there was no follup-up.

Regards,

Chris