I have a custom overlay to map from the Toradex k3-am69-aquila-dev.dtb base that will allow the Aquila SOM to control the VSC8514 quad phy.
I updated the linux kernel /drivers/net/phy/mscc dirver to include the physical address of the phy.
here is the overlay text I am trying to map to the base overlay.
/* ============================================================
* (CPSW/QSGMII fragments for Ethernet Switch Phi)
* ============================================================ */
/*
* Signal | SOM Pin | AM69 V1.1 Func | AM69 V1.1 Pin SoC
* ===================================================================
* ETH_2_QSGMII_RX_N B83 SGMII2_RXN0 SERDES2_RX3_N (AT1)
* ETH_2_QSGMII_RX_P B84 SGMII2_RXP0 SERDES2_RX3_P (AT2)
* ETH_2_QSGMII_TX_N B86 SGMII2_TXN0 SERDES2_TX3_N (AP1)
* ETH_2_QSGMII_TX_P B87 SGMII2_TXP0 SERDES2_TX3_P (AP2)
*
* ETH_2_INT# B81 GPIO0_44 MCASP1_AXR3 (AL33)
* PHY_NRESET# B46 GPIO0_33 MCASP0_AXR5 (AG38)
*
* CPSW9X
* ETH_2_MDC B90 MDIO0_MDC MCASP2_AFSX (AE37)
* ETH_2_MDIO B89 MDIO0_MDIO MCASP2_AXR0 (AC36)
*
* SoC internal pinctrl index
*
* PIN22 → 0x5c → AC36 → MCASP2_AXR0 → SoM B89 → MDIO
* PIN23 → 0x58 → AE37 → MCASP2_AFSX → SoM B90 → MDC
=================================================================== */
/* =================================================================
* RVH ETH_2 QSGMII / VSC8514 final mapping
*
* Physical path:
* RVH VSC8514 copper PHY quad
* -> QSGMII differential pair ETH_2_QSGMII
* -> Aquila SOM pins B83/B84/B86/B87
* -> AM69A SERDES2 lane 3
* -> WIZ2 / SERDES2: /bus@100000/wiz@5020000/serdes@5020000/phy@3
* -> AM69A CPSW9G: /bus@100000/ethernet@c000000
*
* Management path:
* RVH VSC8514 MDIO/MDC
* -> Aquila SOM B89/B90
* -> AM69A MAIN CPSW9G MDIO pins
* -> /bus@100000/ethernet@c000000/mdio@f00
*
* Proven on hardware:
* VSC8514 PHY IDs are strapped at 0x04, 0x05, 0x06, 0x07.
* The active MDIO bus is c000f00.mdio, not c200f00.mdio.
*
* CPSW9G MAC mapping:
* CPSW9G port@5 -> VSC8514 PHY0 -> MDIO 0x04 -> PHY Handle 0x1FE
* CPSW9G port@6 -> VSC8514 PHY1 -> MDIO 0x05 -> PHY Handle 0x200
* CPSW9G port@7 -> VSC8514 PHY2 -> MDIO 0x06 -> PHY Handle 0x201
* CPSW9G port@8 -> VSC8514 PHY3 -> MDIO 0x07 -> PHY Handle 0x202
*
* Critical Linux fix:
* Base DT marks CPSW9G ports as ti,mac-only. These ports are PHY-backed,
* so delete ti,mac-only or Linux phylink/ethtool behaves as MII/PHYAD 0
* and ip link set up can fail with EIO.
* ================================================================ */
fragment@150 {
target-path = "/bus@100000/ethernet@c000000";
__overlay__ { status = "okay"; };
};
fragment@151 {
target-path = "/bus@100000/wiz@5020000";
__overlay__ { status = "okay"; };
};
fragment@152 {
target-path = "/bus@100000/wiz@5020000/serdes@5020000";
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
serdes2_qsgmii_link: phy@3 {
reg = <3>;
status = "okay";
#phy-cells = <0>;
cdns,num-lanes = <1>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
resets = <&serdes_wiz2 4>;
};
};
};
fragment@153 {
target-path = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
__overlay__ {
status = "disabled";
};
};
fragment@154 {
target = <&cpsw0_phy_gmii_sel>;
__overlay__ {
ti,qsgmii-main-ports = <1>;
};
};
fragment@155 {
target-path = "/bus@100000/ethernet@c000000/mdio@f00";
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* Shared VSC8514 reset drive on Aquila B46 / GPIO0_33. GPIO is active-high into MOSFET; MOSFET applies active-low nRESET to PHY.
* Datasheet requires >=2 ms assertion after power/clock stable
* and >=105 ms before SMI/MDIO access after de-assert.
* Use 200 ms margin for bring-up.
*/
reset-gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>;
/* This is a bus-level shared reset for all four VSC8514 PHY addresses. */
/* Assert reset for 10 ms, then wait 200 ms after deassert before MDIO. */
reset-delay-us = <10000>;
reset-post-delay-us = <200000>;
qsgmii_phy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x04>;
#phy-cells = <0>;
max-speed = <1000>;
};
qsgmii_phy1: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x05>;
#phy-cells = <0>;
max-speed = <1000>;
};
qsgmii_phy2: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x06>;
#phy-cells = <0>;
max-speed = <1000>;
};
qsgmii_phy3: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x07>;
#phy-cells = <0>;
max-speed = <1000>;
};
};
};
fragment@156 {
target-path = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
__overlay__ {
status = "okay";
label = "port1";
reg = <0x01>;
phy-mode = "qsgmii";
phy-handle = <&qsgmii_phy0>;
local-mac-address = [00 14 2d d0 2d c1];
/* MAC mux plus shared SERDES2 lane 3 configured as QSGMII. */
phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
};
fragment@157 {
target-path = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
__overlay__ {
status = "okay";
label = "port2";
reg = <0x02>;
phy-mode = "qsgmii";
phy-handle = <&qsgmii_phy1>;
local-mac-address = [00 14 2d d0 2d c2];
/* MAC mux plus shared SERDES2 lane 3 configured as QSGMII. */
phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
};
fragment@158 {
target-path = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
__overlay__ {
status = "okay";
label = "port3";
reg = <0x03>;
phy-mode = "qsgmii";
phy-handle = <&qsgmii_phy2>;
local-mac-address = [00 14 2d d0 2d c3];
/* MAC mux plus shared SERDES2 lane 3 configured as QSGMII. */
phys = <&cpsw0_phy_gmii_sel 3>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
};
fragment@159 {
target-path = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
__overlay__ {
status = "okay";
label = "port4";
reg = <0x04>;
phy-mode = "qsgmii";
phy-handle = <&qsgmii_phy3>;
local-mac-address = [00 14 2d d0 2d c4];
/* MAC mux plus shared SERDES2 lane 3 configured as QSGMII. */
phys = <&cpsw0_phy_gmii_sel 4>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
};
fragment@160 {
target-path = "/bus@100000/pinctrl@11c000";
__overlay__ {
bia5_v11_cpsw9g_mdio_pins: bia5-v11-cpsw9g-mdio-pins {
pinctrl-single,pins = <
/* MDIO */
J784S4_IOPAD(0x5c, PIN_INPUT_PULLUP, 4)
/* MDC */
J784S4_IOPAD(0x58, PIN_OUTPUT, 4)
>;
};
};
};
fragment@161 {
target-path = "/bus@100000/ethernet@c000000/mdio@f00";
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <
&bia5_v11_cpsw9g_mdio_pins
>;
};
};
tdx-info from the SOM
BIA5 - RVH AM69A Headless Image aquila-am69-12594628 ttyS2
Aquila-AM69_RVH-Embedded-Image
aquila-am69-12594628 login: root
root@aquila-am69-12594628:~# tdx-info
Software summary
------------------------------------------------------------
Bootloader: U-Boot
Kernel version: 6.6.119-g8af7a2cb6a06-dirty #1 SMP PREEMPT Tue May 5 11:38:39 AEST 2026
Kernel command line: root=PARTUUID=5a1d15ea-02 ro rootwait console=tty1 console=ttyS2,115200
Distro name: NAME="BIA5 RVH AM69A"
Distro version: VERSION_ID=7.5.0-devel-20260205045228-build.0
Distro variant: -
Hostname: aquila-am69-12594628
------------------------------------------------------------
Hardware info
------------------------------------------------------------
HW model: BIA5 RVH AM69A Embedded Platform
Toradex version: 0211 V1.1A
Serial number: 12594628
Processor arch: aarch64
------------------------------------------------------------
my question is:
Q1. If we have recently moved from Aquila AM69 V1.0 to Aquila AM69 V1.1, should the base overlay change from k3-am69-aquila-dev.dtb?
* gpiochip | line | AQUILA Pin Name | RVH function | direction | active
* ===================================================================================================
* AQUILA_A11 GPIO_11_CSI in high
* gpio2 1 AQUILA_B17 1V8-PG in low
* gpio2 2 AQUILA_B18 SD-1-PWR-FLT in low
* gpio1 48 AQUILA_B19 3V3-ISO-EN out high
* gpio2 12 AQUILA_B42 56V-EN out high
* gpio2 31 AQUILA_B43 2V5-PG in low
* gpio2 13 AQUILA_B44 1V0-PG in low
* gpio2 18 AQUILA_B45 3V3-ISO-FLT in low
* gpio2 33 AQUILA_B46 PHY_NRESET# out low
* AQUILA_B57 EEPROM-WE out high
* gpio2 16 AQUILA_B58 EXT-LED3 out high
* gpio1 32 AQUILA_C01 EXT-LED1 out high
* gpio1 33 AQUILA_C02 EXT-BTN1 in low
* gpio1 37 AQUILA_C03 BMA400_INT in high
* gpio1 39 AQUILA_C04 56V-PG in low
* gpio1 17 AQUILA_C20 NET8 in low
* gpio1 29 AQUILA_C21 TPM-SPI-CS out low
* gpio1 30 AQUILA_C22 TPM-PIRQ in low
* AQUILA_C23 TEMP_ALT in high
* AQUILA_C24 PSE_INT in low
* gpio2 25 AQUILA_C25 BTN-LED out high
* gpio2 24 AQUILA_C26 RFM_RST out low
* gpio0 49 AQUILA_D06 RFM_IRQ in low
* gpio2 34 AQUILA_D23 NET1 in low
* gpio2 17 AQUILA_D24 NET2 in low
* gpio2 29 AQUILA_D25 NET4 in low
* ==============================================================
