Reset conditions during the reset

Dear Sir or Madam,
currently we are trying to integrate the Colibri board iMX6DL in our devices.

Unfortunatelly there are some uncertainties concerning the input/output states in reset mode.
The reset conditions immediately after the reset are clearly described in Table 91
(Data sheet Technical Data; IMX6SDLIEC Rev.5).

But what are the input/output states of all signals during the reset?
(“nRESET_EXT” = LOW , power supply is still applied!)

Some of the signal states are described in table 92 (Data sheet Technical Data; IMX6SDLIEC Rev. 5).
But this only seems to refer to the Signal differing before reset and after reset state.
Does this also apply to the signal states “during” the reset or do those signal states only refer to the states before executing the reset?

What about the remaining signal states?

Thank you very much.

The reset states of the signals that can be found in table 91 are indeed only guaranteed at the moment the reset is released. After that event, the boot loader or OS can change the state. In the time before releasing the reset, the situation is a bit more complex.

As soon as the main voltage is applied to the module, the PMIC is starting to ramp up the different rail. The supply for the IO blocks of the SoC is one of the last voltages that is coming up. If the RTC battery is present, it takes a bit more than 5ms between applying the main voltage rail and enabling the IO block rail. Without an RTC battery, it takes longer since the PMIC need to initialize first.

As you have seen in table 91, most of the pins are by default configured as inputs with an pull up resistor enabled. As long as the IO block supply is not present, the pins cannot be pulled up to a non existing voltage. There might be some back feeding on the IO block rail. This means the state of the pins is completely non deterministic during this power up sequence.

10ms after the IO block voltage is applied, the reset is released. Even tough, NXP does not specify the state of the pins before releasing the reset, we have observed that the pins are already pulled up during the 5ms between applying the IO block voltage and releasing the reset signal.

We know, that for some applications, the undefined state of the pins during the power up sequence is not acceptable. There are several workarounds:

  • The easiest one is adding an external pull down resistor. I recommend a resistor between 1k and 10k. overdrives the internal 100k pull up resistor, even during the power up of the IO block
  • Gating the critical pins by using the nRESET_OUT which is defined from the beginning.
  • Using one of the signals in table 92 which have a defined low state also before the reset is released.