Recommended soft switch hardware

Technical Support
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1

Working on a Verdin iMX8M Plus carrier board design. The design guide states in Section 3.3.10, “If the main module power rail is removed in any power state, the different power rails are shut down in a non-graceful order. This should not physically damage the module. However, the flash memory may get corrupted. Therefore, removing the VCC should be avoided if the system was not shut down properly in advance.”

The first question is, how risky is this? I am reaching out to our software engineer to confirm if we are booting from the Flash or from the uSD card. I expect if we are not booting from FLASH, then the damage from corruption would be minimal?

From the design guide, the family specifications, and the datasheet do not give timing diagrams for the power-down sequence. How long does a power-down sequence take?

Does Toradex have a simple, recommended circuit (single IC ideally) that can help with this functionality?

I have designed complex soft-power-down circuits before for other designs. However, we really don’t want to be that complex. When the user hits the power-down switch, the system will turn off. If there is a small delay from when the power switch is switched off to when the power FET is actually turned off, that is okay. That is also easy to implement…but I don’t think that will work within the Toradex architecture.

I would connect that ‘early’ detection signal to PWR_BTN_MICO# (in theory) to go from the Running State to the Off State. However, that signal would be low forever once the power switch was turned off. It seems the SOM would be waiting for it to go high to determine if it is a shut-down commend or a Force Off command?

From the Power Management signal descriptions, it is not clear to me if the PWR_BTN_MICO# signal going high would turn on the module. However, on the State diagram, it looks like just VCC turning on is required?

This is the last aspect of our hardware design that has any questions and we are eager to get our carrier board on order. Thank you in advance for prompt assistance.

Best Regards,
Ben

2

Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!

Did you like my answer?

:+1: :-1:

Hello!

Thank you for your inquiry regarding the power management and shutdown procedures for Toradex modules. Let me provide you with some insights based on the documentation.

  1. Flash Corruption Risk: It’s important to note that removing VCC without a proper shutdown sequence can lead to flash memory corruption. However, this action will not physically damage the module. For more details, you can refer to the Carrier Board Design Guides.

  2. Power-down Sequence Timing: After the power rails are removed, there might be a delay of several seconds before the CTRL_FORCE_OFF_MOCI# signal goes low. This timing is crucial for ensuring a safe shutdown process. More information can be found in the Verdin iMX8M Plus Mezzanine documentation.

  3. Recommended Circuit: The Verdin Development Board uses a “switched VCC approach” with a power button control IC. This setup:

    • Utilizes CTRL_FORCE_OFF_MOCI# to switch off VCC after the module shutdown.
    • Includes a button control IC for managing the main VCC switching.
    • Connects an interrupt output to CTRL_PWR_BTN_MICO#.
      You can explore this design further in section 3.4.1 of the Carrier Board Design Guide.

  4. PWR_BTN_MICO# Behavior:

    • A short press (less than 5 seconds) powers up the module from the “Module OFF” state or wakes it from sleep.
    • A long press (more than 5 seconds) initiates an immediate shutdown.
    • The module automatically transitions to running mode when VCC is applied.
      For more details, please refer to the Verdin iMX8M Plus module documentation.

For your specific implementation, reviewing the Verdin Development Board’s switched VCC approach is highly recommended, as it provides a reliable reference design.

If you have any more questions or need further clarification, feel free to ask!

Best regards,
Toradex AI Assistant

3

This confirmed a couple items (such as turning on when VCC first applied), however doesn’t address some of my more complex questions. Please advise.

Thanks,
Ben

4

Not exactly. The “flash” used on the Verdin module is actually an eMMC chip, which has a very similar internal structure to an SD card (for example, a NAND flash array managed by an internal flash controller).
The flash controller is responsible for:

  • Flash Translation Layer (FTL) management
  • Command processing and protocol compliance
  • Wear leveling and endurance optimization
  • Security features
  • Error correction and data integrity

Additionally, we use a journaling file system like EXT4, which adds another layer of protection for data integrity.
As a result, in most cases, an abrupt VCC (power) removal does not cause file system corruption, although any data being written at that exact moment may not be fully saved.

However, none of this guarantees 100% data integrity in the case of frequent or repeated abrupt VCC removals.
Reliability data for EXT4 or other journaling file systems can be found publicly on the Internet, while detailed information about eMMC internal algorithms is usually kept confidential by eMMC manufacturers.

Minimizing data write operations or performing them only on external media, such as an SD card, further reduces the risk of OS corruption to an absolute minimum.
However, a graceful OS shutdown remains the most reliable way to ensure data integrity

5

You don’t need a complex soft-power-down circuit to perform a graceful power-off. Even in a very simple design, like the one shown in the picture below, short grounding of the PWR_BTN_MICRO# signal while the system is running state generates a software interrupt. Depending on the operating system settings, this either initiates a software-controlled shutdown or opens a menu allowing the customer to choose an action.

The OS shutdown time depends on the OS configuration but usually takes just a few seconds.
Pressing the power button for longer than 5 seconds forces the system to shut down immediately, bypassing software control.

You can keep external Vcc applied during shutdown; Then all internal power rails on the module (except for the RTC) will be switched off.
If the system is in the OFF state (but Vcc is still present), pressing the power button again will initiate the power-on sequence.

Additionally, to allow the system to boot automatically when only Vcc is applied, the module includes an internal pulse generator that simulates a CTRL_PWR_BTN_MICRO# signal when the Vcc rail transitions from no power to active Vcc.

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Could you please list all your remaining, more complex questions?

6

My initial response (needing the more complex questions answered) was with regard to the first, BOT reply. You have answered many of those already.

You have confirmed what I thought, we need to setup for a smooth shutdown. We are at risk if we regularly just turn off power.

One thing in your responses (and the setup for the SOM) that is the issue is that we do not have a power button, we have a power switch. That is based on system we are working with, we will not have a power button. This is not a design element we have freedom to change.

On our carrier board, as the design exists right now, that switch turns on an N-channel FET which then turns on the main P-Channel power FET to enable power to the entire carrier board. The SOM, being on 5V will be the first thing that is powered up, before the 3.3V and 1.8V power supplies will be enabled.

When the power switch is turned off, the N-channel FET will turn off and turn off the P-channel FET which will then turn off power to the board. So, for the entire power control functionality, I need three things:

  1. When the switch is turned on, it needs to turn the main P-FET on quickly to turn on power to the board. We don’t want to have a long delay from the time the power switch is turned on until the time the unit turns on. Goal is for t-on <1s.
  2. When the switch is turned off, first, it needs to have a delay (of a few seconds) between when the switch is turned off and when the P-FET gets turned off. It sounds like the goal is for t-off =3s would be good. However, for designing the circuit, it would be good to have an exact value for this timing. If the time is too long, if the user quickly turns the unit back on after turning it off, the device ends up in a stopped state with no way (with our hardware) to recover.
  3. When the switch is turned off, it needs to send a pulse to PWR_BTN_MICO to tell the SOM to go into shutdown mode. Note: This PWR_BTN_MICO pulse must happen quickly so that is can be ‘ahead’ of the delayed turn-off of the main FET.

That is what I mean by more complex functions.

One additional question I had not asked before. What should the delay be between the SOM receiving power and the 3.3V or 1.8V power supplies turning on?

Thanks!
Ben

7

Sorry, but I’m not sure I fully understand your reasoning regarding N- and P-channel MOSFET control in relation to graceful shutdown.
If you have no control over the external power switch design but can modify the carrier board, I would recommend adding a supercapacitor large enough to keep the module running for approximately 5 seconds.
You don’t need to include a physical PWR_BTN; instead, simply monitor the external power and pull the PWR_BTN_MICO# line low for a short duration (around 0.5 seconds) to initiate a proper OS shutdown.
If a physical PWR_BTN is required, you can simply disconnect it when power is cut to prevent user interaction during shutdown.

Note: The timing between VCC and the internal power rail ramp-up is module-dependent.
For Verdin iMX8M Plus:

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8

While I appreciate the thought, hold up capacitors are only necessary when power will be pulled abruptly. That is not the expectation for our system.

Back of the envelope calculations show that a Super capacitor to hold up voltage at 2A (5V, 10W total power) for 5s would need to be on the order 10F and would be prohibitively large. And, that would require extra power supply circuitry to charge it properly without causing major surge currents on the input power or power supply, while allowing it to power the system.

Here is our power-control circuit. The power switch has the 12V input that turns on Q56 when the power switch is moved into the on position which then turns on Q55 to turn on power to the system.

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The problem is that it turns power off just as abruptly.

At this point, it does not seem as if you have an existing solution to delay turning off the power circuitry when the power switch is turned off. The Toradex designs count on a power button. No problem. We can close that aspect of the discussion. I have a solution for that I have used in the past. It is not as simple as I might like, but it is not overly cumbersome. Once I figure out exactly what we need for power-up and power-down timing/sequencing, I can implement that.

9

I want to make sure I fully understand the timing information you sent me and confirm what I think is the desired power-up sequence.

Previously I was told that the SOM has no ‘preference’ for voltage anywhere in the range of 3.135V to 5V. Does the SOM have switching regulators on it for all power generation? That would explain why the voltage range really doesn’t matter. I just want to confirm that the power consumption is the same independent of VCC voltage. I can supply VCC with 3.3V or 5V but want to do so in the most power efficient way. Please confirm/advise.

Under the assumption that 5V is just as efficient as 3.3V, I plan to use 5V for the SOM VCC. Under that setup, when our power switch is turned on, it turns on our 5V regulator which would then turn on power to the SOM.

From the timing table you gave, it appears all the SOM power supply modules are ready 94ms after power is given to VCC. Thank you for that power-up sequence information.

It also seems as if the best way to power to the rest of my board would be to wait to enable subsequent power supplies (3.3V and 1.8V) until after 68ms, using the CTRL_PWR_EN_MOCI signal, correct?

Last, for when I want to power-off the system, rom this chart, it looks like I do have to make the PWR_BTN_MICO a low pulse.

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Am I correct? Do I have to pulse PWR_BTN_MICO low? I don’t want to add the extra circuitry to make it a pulsed signal if I can help it. However, I do want to SOM to start the power down process as soon as PWR_BTN_MICO goes low.

Under the assumption that I am correct, I have one implementation method I can consider. First, can I used another GPIO (not PWR_BTN_MICO) to initiate a software shutdown? And, if I am not able to do that, can I use a GPIO to have the SOM generate it’s own PWR_BTN_MICO low pulse?

Thanks for all your help!
Ben

10

Yes, all that explained at Verdin iMX8M plus datasheet:

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You need to rely on the presence of the CTRL_PWR_EN_MOCI signal rather than specific timing.
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Yes.

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Yes, but OS reconfiguration will be required.
However, why do you prefer this approach? What advantage does it offer over using the PWR_BTN_MICO#?

11

I would keep PWR_REV_PROT directly connected to the module’s VCC. Use CTRL_PWR_EN_MOCI to control the carrier board power, and configure POWER_SE_ON to generate a short negative pulse on PWR_BTN_MICO# each time its state changes. The design is simple, and if “the user quickly turns the unit back on after turning it off”, nothing bad happens because the module ignores PWR_BTN_MICO# pulses until full shutdown.

12

Thank you for the power supply information. Also, I understand that I do not need to rely on the 68ms, I will just use the CTRL_PWR_EN_MOCI signal. I asked about the 68ms to make sure I was interpreting the table you sent me correctly. :slight_smile:

When my power switch turns off the <POWER_SW_ON> signal does not pulse, it turns off, period. I need extra hardware to generate a pulsed signal. How complex is the OS reconfiguration? Is that something my software engineer will be able to easily figure out?

Unfortunately, POWER_SE_ON is connected to a power switch and can only be high or low. It can not pulse.

In terms of the user turning the switch on-and-off, this is a user interaction issue, not a SOM issue. The way the power switch works (since it is a switch, not a button) is, if the user turns the unit back on before the shutdown has been completed (and the power supply has truly been turned off), the SOM will still be in shutdown, but VCC will be fully powered. VCC is turned off based on the time (5-10s) delay I ‘configure’ in hardware. The user will expect the unit to be on even though the SOM is off.

We don’t however need to fully engage in those details.

With the exception of possible additional details regarding the OS reconfiguration required, I believe that I have all that I need to properly setup the hardware to prevent an abrupt shut-down and meet all my other needs. Thank you for your help!

Best Regards,
Ben

13

It’s not very complex, but it does require some prior knowledge or research.
Sorry, I’m not familiar with your software engineers, so I can’t assess whether it will be easy for them or not.

14

Fair enough. I should have asked, if it was something complex that a general software engineer should be able to do. :slight_smile:

I did speak with him briefly and we determined that the back-up plan is that I send the GPIO into the SOM and then send another output connected to FET to briefly ground PWR_BTN_MICO# so that the SOM can then generate the short pulse required.

Thanks!

15

Please check this article - gpio-power-management-keys

16

Thanks for the link!