I’d know if someone had use QSPI module on iMX7S with FPGA and not just with a flash device,please, because I found in IMX7SRM.PDF the details just for a flash device, if it’s possible to found something about FPGA it’s will help me a lot.
Hi @ImaneCh !
It is certainly possible to communicate between the module and an FPGA device. You need to be sure that your FPGA device is capable of that.
From our Colibri iMX7 datasheet at chapter 5.25 you can find the pins available for SPI communication.
And you might want to use the SPIDEV to communicate with your FPGA device. Please refer to SPI (Linux) | Toradex Developer Center. For Colibri Evalboard you will need to refer to this section to enable it: SPI (Linux) | Toradex Developer Center
We have Windows Embedded Compact 2013 (WEC2013)Toradex IMX7S.
This microprocessor will have a QuadSPI link with an fpga but we are unable to configure the clock source.
We tried to configure it as follows, the picture below
Below the detail of the functions
We configured (CCM_TARGET_ROOT85 and CCM_CCGR21) with these functions, but we don’t have anything in our scope.
Thank you for answer.
Best regards, Imane.
I’d recommend to use the Toradex WINCE lib function
BOOL Imx7Clk_EnableClock (HANDLE hClk, tImx7ClkId clockId, BOOL enable)
This library “clklib.lib” is compatible with QuadSPI i.MX7?
The clklib.lib is compatible with Colibri IMX7. And you can control QSPI clock. All supported clocks are listed at clk_imx7.h from library package. Unfortunately we have no dedicated library for QSPI communication.
Do you have an example of a QSPI configuration without the use of the library?
I configured with different functions available on the internet but I’m not sure if it can work, could you please enlighten me on this?
Sorry but we never tried to use QSPI. And we have no examples.
I’m suprised of your last answer. Does it means that QSPI was never functionnaly tested by Toradex on the imx7s module ?
It was tested on imx7s module. But using Linux.
Is the driver for linux available?
Regarding TS question, “because I found in IMX7SRM.PDF the details just for a flash device”. The main QuadSPI feature is memory mapping any flash device or set of up to 4 flash devices and read only accessing them as a contiguous memory without any manipulations with interrupts, registers or DMA.
But indeed it can be used for any read only and write only transfers. Simultaneous I/O like in eCSPI is not possible, I mean no way to send and receive bit of data on the same SCK pulse. QuadSPI LUT table is programmed to execute sequence of QuadSPI commands like “send address”, “read data”, “write data”, “read data DDR” etc. Obviously LUT command sequences can be crafted for FPGA I/O and any other unsupported QSPI device. Best read from FPGA performance can be achieved using QuadSPI the way it was dedicated for, memory mapped read only device. No problems if your FPGA just sends data, just read next cell from dedicated QuadSPI memory window. Usage of read only mode doesn’t prevent issuing write commands from time to time, but performance will be much worse and CPU consuming.
Linux spi-imx-qspi.c driver seems supporting only memory devices, spi ctrl->mem_ops is implemented, but not ctlr->transfer, ctlr->transfer_one or ctlr->transfer_one_message. Instead of fast and CPU-less automatic flash memory read out in AHB mode to memory window (256MB on iMX7), this driver issues IP commands for every read and write.
Since I’m quite familiar with QuadSPI on VF family devices, it’s quite clear for me what I would do next with FPGA project. But I’m not sure what to suggest for you. Is it an option to move QSPI to M4? What are your FPGA access requirements? If just read, then what about setting QSPI from M4 and devmem data to Linux? Could you emulate flash memory device on FPGA? …