Pin muxing on M4 for making GPIO1_IO11 an output

We got this from Stefan for muxing the LED 0 - SODIMM135 GPIO1_02

gpio_config_t gpioLed0 = {
    "SODIMM135",                      	  /* name */
    &IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02, /* muxReg */
    0,                                  	/* muxConfig */
    &IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02, /* padReg */
    0,                                  	/* padConfig */
    GPIO1,                              	/* base */
    2                                   	/* pin */

And everything seem to be there until GPIO1_IO08. When we would like to set the multiplexing for GPIO1_IO11 for example or any other bit greater then 7 we are not able to figure out what the muxConfig and the padConfig should be for LED3 SODIMM67 GPIO1_IO11

gpio_config_t gpioLed3 = {
    "SODIMM67",                      			/* name */
    IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG,       /* muxReg */
    0,                                  	    /* muxConfig */
	&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11,  		/* padReg */
    0,                                  		/* padConfig */
    GPIO1,                              		/* base */
    11                                   		/* pin */

Question would be what is the recipe for finding out the muxConfig and padConfig values so that we will be able to route any pin to one of its alternate functions.

Any help would be appreciated, pointers to freescale/nxp samples are warmly welcomed, samples … priceless.

We figured out the muxing settings for the GPIO4_IO17 (SODIMM103 on IMX7D Pin 15 of the Iris X16 connector) so we are posting it here in case somebody might need it.

gpio_config_t gpioLed417 = {
     "SODIMM103",                                                                      /* name */
     &IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI,                   /* muxReg */
     5,                                     /* muxConfig */
     &IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI,                   /* padReg */
 	IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS(2)  | 	       /* padConfig */
     GPIO4,                             /* base */
     17                                    /* pin */

Page 2114 of the IMX7DRM contains some of the information needed for muxing … we still do not know how to make up the padConfig …

Sorry for the delay, somehow this question did not made it into the i.MX 7 queue.

The GPIO structure is just a helper struct used in examples, the individual fields are mainly concerning two IPs: The IOMUXC and the GPIO controller.

The IOMUXC deals with all pads and their exact functionality (one of them is GPIO, most pins have 6 other functionalities). Each pin has at least two register: One register which deals with the pin functionality (muxReg), one one which deals with the pad settings (padReg). Chapter 8.2 in the IMX7RM has a description of both registers. The Colibri iMX7 datasheet, Chapter 4 has a list which allows to translate between SODIMM number and the i.MX 7 Ball Name. The Ball Name (e.g. I2C4_SDA, SODIMM 75) can be used to lookup the pad in the IMX7RM, or it can be directly used to search for the appropriate muxReg/padReg (IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA/IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA, see platform/devices/MCIMX7D/include/MCIMX7D_M4.h). All pads seem to use the first mux as GPIO (muxConfig). The padConfig depends on the electrical characteristics you expect. Most pads have the same options, Chapter 4.2 (Table 4-3) of the Colibri iMX7 reference manual shows the pad control options. The MCIMX7D_M4.h has prepared macros.

To use SODIMM 67 (i.MX 7 Ball Name GPIO1_IO11 ) as GPIO your configuration should look like this:

  gpio_config_t gpioLed417 = {
      "SODIMM67",                                          /* name */
      &IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11,                   /* muxReg */
      0,                                                   /* muxConfig */
      &IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11,                   /* padReg */
      IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS(0)  |            /* padConfig */
      GPIO1,                                               /* GPIO bank base */
      11                                                   /* Pin within GPIO bank */

This enables a 100kOhm pull down and hysteresis.