Pin function multiplexing on Colibri iMX8X with TorizonCore Builder

Dear Community,

some of the 200 pins of the Colibri iMX8X SODIMM interface (X1) are connected to 2 balls of the processor as explained in its datasheet paragraph 4.1 “Function Multiplexing”. Pins X1.67, .97 and .101 are of those and I need to use them as PWM.D and GPIOs on my board.

If my understanding is correct, they are all used by CSI ALT0 function by default (datasheet par. 4.4.1), then I have to use Device Tree and TorizonCore Builder to reconfigure them, paying attention to “make sure that the unused pin of each multiplexed pair is tri-stated or configured as input to avoid undesired behaviour and/or hardware damage” as written in the datasheet.

I think the relevant sections of imx8qxp-colibri.dtsi are the following:

        /* Colibri PWM_D */
		pinctrl_pwm_d: pwmd {
		/* both pins are connected together, reserve the unused CSI_D04 */
			fsl,pins = <
				IMX8QXP_CSI_D04_CI_PI_D06			0x61		/* SODIMM  67 */
				IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT		0x60		/* SODIMM  67 */
			>;
		};

and

		pinctrl_hog1: hog1grp {
			fsl,pins = < [...] IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x20		/* SODIMM  97 */
				IMX8QXP_CSI_D03_CI_PI_D05			0x61		/* SODIMM  97 */ [...]     				IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28		0x20		/* SODIMM 101 */
				IMX8QXP_CSI_D00_CI_PI_D02			0x61		/* SODIMM 101 */
			>;
		};

First question: is it fine to use simply a device tree overlay for this type of reconfiguration on multiplexed pairs? Can I proceed as with “normal” unpaired pins?

Second question: I cannot find where the parallel CSI is enabled in device tree files with something like status = “okay” to disable it. Is really enabled by default?

Thank you for the attention and the help in handling this configuration.

Best regards,

ldvp

Greetings @ldvp,

I feel there’s a misunderstanding here or perhaps I’m misunderstanding your issue.

So just to summarize you want to use SODIMM 67 as a PWM D and you want to use SODIMM 97 & 101 as GPIOs. Is that correct?

If so then these pins are already defaulted to these functions.

SODIMM 67 is assigned to PWM D here: http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi?h=toradex_5.4-2.1.x-imx#n688

While SODIMM 97 & 101 are used as GPIOs here: http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi?h=toradex_5.4-2.1.x-imx#n571

So everything should be good to go by default, if I understand the situation here correctly. But please correct me if I misunderstand still.

Best Regards,
Jeremias

Hi Jeremias,

thank you for the answer and the information, first of all I confirm your understanding is correct and the pins are indeed working as GPIOs and PWM by default as you write.

I was misled 1) by gpioinfo output by torizonextras/arm64v8-gpiod where the two 97 and 101 GPIOs are “unnamed” (see attachment, the others I used previously are all named like SODIMM_XX) and 2) by a wrong connection on the external hardware, which was connected to PWM.B and not PWM.D in system wirings.

By the way, can you provide a feedback about the first question “is it fine to use simply a device tree overlay for this type of reconfiguration on multiplexed pairs? Can I proceed as with “normal” unpaired pins?”

Thanks again for the help and best regards,

ldvp

By the way, can you provide a feedback about the first question “is it fine to use simply a device tree overlay for this type of reconfiguration on multiplexed pairs? Can I proceed as with “normal” unpaired pins?”

Yes overlays should be fine for this purpose. As long as you define the paired pins properly as they are in the source device tree.

Best Regards,
Jeremias