Options for Tianma Type display


I’m trying to integrate the Toradex Tianma adapter board with my custom carrier board design and had a few doubts regarding some of the “options” for the operation of the display. I’ll be using a Colibri i.MX6 DualLite IT with the latest version of the Linux BSP(2.6.1 right now I believe). The Display I’ll be using is pin compatible with the Zettler ATM0700D6C which you guys have tested with the Tianma Adapter PCB. The datasheet for my particular model can be found here: http://www.azdisplays.com/PDF/ATM0700D6J.pdf

Here are my doubts:

  1. DE/SYNC mode: From what I see in your design, clocks have been provided for HSYNC and VSYNC, and the DE pin has been connected to LCD_BIAS and tied to ground. So I’m guessing the display is being used in SYNC mode? If so, what purpose does the LCD_BIAS signal servee? Are any changes required in the kernel to use the display in this mode?
  2. DITHER function: According to the datasheet this option is normally disabled, what do you guys recommend?
  3. UD/LR: What is the scanning direction used by the kernel? Up to Down and Left to Right or something else?
  4. Reset Signal: What is the purpose of resistor R149 (in my design shown below it is R25) in the Schematic for the Tianma Adapter, between nets LCD_DISP_C and RESET_OUT_C#. Should I assemble this and what resistance value should I use if so?
  5. Backlight Control: To disable backlight control and have 100% brightness all the time, I’ve removed the BL_ON and PWM_A inputs to the PAM2841 in the design and tied COMP to ground like so. Is this correct?
  6. VCOM: There is a choice between connecting VCM on the TPS65105 and +3.3V, am I correct in assuming this should remain connected to the TPS?

If any further details are required to answer my queries please let me know. Thank you for your time and support.

Added some inline screenshots for clarity.

Hello! Are there any updates on this question? These are the last few doubts I have in my design. I can move ahead once they’re cleared. I’d really appreciate the help!


  1. DE/SYNC mode.

By default HSYNC/VSYNC and DE signals are generated.
So, since your LCD seems to require either one or the other but not both
you could

  • decide on what you want to use and only connect that one. Probably
    having zero Ohm resistors to make that a stuffing options.

  • change the device tree, so that only one of HSYNC/VSYNC or DE signals
    is muxed to the pins.


This is the name used on the PXA SOC for a pin which was able to output
the DE signal and something called BIAS. So this pin outputs the DE signal.


You will have to try and check what looks better with your UI.

  1. UD/LR: What is the scanning direction used by the kernel? Up to Down and Left to Right or something else?

The module draws a frame starting with the top line and drawing lines from left to right. So I expect that the setting for Up to Down and Left to Right is the right way to go.

  1. Reset Signal

LCD_DISP may be positive or negative logic depending on the connected display. So you would either stuff R25 or stuff R15/T2 or, if you do not want
to assert the LCD Reset from the modules Reset you would stuff only R15.

  1. Backlight Control

Unconditionally connecting ENA to 3.3V and connecting a 100nF from COMP to GND looks correct.

  1. VCOM

Probably it is better to keep it on VCOM, however that is probably for @satyan.tx to answer.


Hello Max,

Thanks for the information! I appreciate the help.