Offset in main oscillator in imx7d

We found that all our imx7d modules (2 512MB and 20 1GB) use main oscillator with offset – 24.004MHz, while it is marked “24.000” as required. Because of this we can’t use PLL outputs for Ethernet (output is 50.008MHz, which is outside of specification). USB seems to work, but as I understand it is too outside the specification. Are you aware of the problem with your oscillators, what are you going to do with it? We have measured with freshly calibrated active probe, which is withing 7 digit true for reference 10MHz signal.

hello @aystarik and Welcome to the Toradex Community!

Could you provide the version of the Hardware and Software of your module? Which carrier board are you using?

Because of this we can’t use PLL outputs for Ethernet (output is 50.008MHz, which is outside of specification)

Did you measure the frequency of the Clock on the PHY? Are you having any Issues regarding Ethernet?

Best regards,
Jaski

for NAND modules “Col iMX7D 512MB V1.1D”
for eMMC modules “Colibri iMX7D 1GB V1.1A”
Carrier is “Col Evaluation V3.2B”

PHY on your modules is fed from the 50MHz MEMS generator, not from PLL and main clock, so it’s frequency is exact and irrelevant. We export MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 for second ethernet port, and there is 50.008MHz instead of 50.000 needed.

Hi, Thanks for this Information.

We export MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 for second ethernet port, and there is 50.008MHz instead of 50.000 needed.

Have you seen any issues due to that?
Could you share your devicetree changes?

Thanks.

I have an issue that frequency which is supposed to be less than 50 ppm is 166 ppm error at room temperature/new. Why in hell do you want my device tree changes? PLL for ENET subsystem is fixed and I am talking to you about HW issue on your modules, not a SW misconfig.

Hi @aystarik, noted, thanks for sharing the details of your setup. We will check internally and get back to you, as certainly this can lead to issues.

We export MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 for second ethernet port, and there is 50.008MHz instead of 50.000 needed.

Quite straightforward. Did you happen to see the same issue for the first Ethernet?

The device tree changes are simply asked in case there has been some configurations errors there as this pin can be multiplexed: imx7d-pinfunc.h « dts « boot « arm « arch - linux-toradex.git - Linux kernel for Apalis, Colibri and Verdin modules

By sending us your device tree changes we will be able to replicate your exact hardware definitions with no margin of error.

I believe you are making measurements directly in X1_106? Any further comment of your environment (as we further check with our known configuration) will be greatly appreciated.

Thanks and regards,
Alvaro.

Noted, thanks for the further comments. We have our HW engineers checking on this and they will directly update this thread with their findings. Thanks for reporting this in any case.

I already mentioned that your first ethernet PHY uses external MEMS generator to make 50MHz, so it is not possible to drive this pin with PLL output without using soldering iron on the module. I already traced the problem to the crystal you are using – main one of 24.000 MHz is really 24.004 MHz. In order to validate anything I’m saying you can just measure frequency on it on any of your modules without any software loaded.

Hi @aystarik

You are right. Thanks for investigating and communicating this issue. We are sorry for the inconvenience.

This issue will be solved in the next revision of the hardware, where the release date is not defined yet.
Additionally we will document this issue in an errata and in the next version of the datasheet of the module.

Depending on your requirements, we suggest you to use an external oscillator on your custom carrier board for the clock source of the second Ethernet PHY.

Best regards,
Jaski