I am trying to get the 5th UART working and have made the following changes to the device tree
imxx6qdl-apalis.dtsi
added
uart3 { /* New for 5th UART on Apalis IMX6 efs */
pinctrl_uart3_dce: uart3-dcegrp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3_dte: uart3grp-dte { /* DTE mode */
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1
>;
};
};
Commented out DTR and DSR in UART 1 (Although I believe this to be unnecessary as it is before UART 3)
uart1 {
pinctrl_uart1_dce: uart1-dcegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart1_dte: uart1-dtegrp { /* DTE mode */
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
>;
};
pinctrl_uart1_ctrl: uart1-ctrlgrp { /* Additional DTR, DSR, DCD */
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
/* MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 */
>;
};
};
Added
&uart3 {
pinctrl-names = "default";
#ifndef USE_UART_IN_DCE_MODE
pinctrl-0 = <&pinctrl_uart3_dte>;
fsl,dte-mode;
#else
pinctrl-0 = <&pinctrl_uart3_dce>;
#endif
status = "disabled";
};
Added the following to imx6qdl-apalis-ixora.dtsi
&uart3 {
status = "okay";
};
The UART shows up in /dev, but no activity on the pins. Am I missing something for this to work?