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Hello! I understand you need to generate PWM signals at higher frequencies (20 kHz–200 kHz) on the Verdin iMX8M Plus for a backlight driver, but you’re seeing a much lower maximum frequency in Yocto. Let’s go through what you can do to achieve these higher PWM output frequencies.
1. Hardware & PWM Channel Availability
First, please note that the Verdin iMX8M Plus exposes three PWMs:
- PWM_1:
/sys/class/pwm/pwmchip0/
- PWM_2:
/sys/class/pwm/pwmchip1/
- PWM_3_DSI (for display backlight):
/sys/class/pwm/pwmchip2/
(source)
If you require four independent PWMs, additional configuration or alternative pins may be necessary as only three are directly available.
2. Why Are You Limited to 300 Hz?
The frequency of a standard Linux PWM interface is determined by the period you set via sysfs (or another interface), and the minimum period is limited by the input clock to the PWM controller and its hardware prescaler. When the input clock is low, the achievable frequency is also low.
Most often, device tree settings define the input clock source and frequency for the PWM controllers. If you’re limited to low frequencies like ~300 Hz, it likely means the PWM controller is being clocked from a low-frequency clock source (like a 32 kHz or 24 MHz oscillator) and/or the prescaler is set incorrectly.
3. How to Change the PWM Clock Source or Frequency
a. Device Tree Adjustments
To use a higher-frequency clock, adjust the device tree to assign one of the SOC’s MHz-level clocks as the input to the PWM block. This involves:
-
Locating the PWM Node
Find the relevant PWM node in your device tree (commonly imx-pwm.*
nodes).
-
Assigning the Correct Clock
Check the clocks = <&clk>;
property on the PWM node. Assign a high-speed clock (such as 24 MHz or higher), if available.
-
Example (device tree fragment):
&pwm1 {
clocks = <&clks IMX8MP_CLK_24M>;
...
};
Replace IMX8MP_CLK_24M
with the appropriate high-speed clock for your SoC.
-
Rebuild and Deploy the Device Tree
b. PWM Configuration via Sysfs
Once the correct clock is set, you can use the sysfs interface to set the period:
cd /sys/class/pwm/pwmchipX/
echo 0 > export
# For 100 kHz: period = 1/100,000 = 0.00001 s = 10,000 ns
echo 10000 > pwm0/period
# For 50% duty cycle:
echo 5000 > pwm0/duty_cycle
echo 1 > pwm0/enable
(reference)
If the kernel still doesn’t allow such a short period and reports an out-of-range error, the input clock and/or prescaler setup remains insufficient and device tree/source code further adjustment is required.
c. Limitations
- The PWM controller has a 16-bit counter and a 12-bit prescaler (source), so maximum frequency is still limited by the counter size and the input clock speed.
- You can calculate the maximum achievable frequency as:
f_PWM = clock_in / (prescaler * period_cnt)
With maximum clock and minimal prescaler.
d. Reboot
After rebuilding and deploying the new device tree with the faster clock, reboot the board and re-try configuring the high-frequency PWM.
4. Summary
- You need to set a high-frequency clock as the source for the PWM controller in the device tree.
- After adjusting, you can achieve periods as low as your hardware allows, sufficient for 20–200 kHz output.
- Only three hardware PWM channels are available on Verdin iMX8M Plus—test if these suffice for your application.
For more detailed device tree setup, please see:
If you need a concrete device tree file example, let me know your current one and I can help further.
Best regards,
Toradex AI Assistant.