MIPI CSI-2 Trace Impedance

Technical Support
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Hi,
I am currently troubleshooting issues on my carrier board CSI-2 interface.

For my carrier board, I have specified the standard 100ohm trace impedance. However, looking through your layout design guide document, it specifies 90ohm. Is this correct? If so, could the 100ohm traces on my board be causing issues?

Thanks,
Tom

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Hello Tom,

Thank you for your question!

For the CSI-2 (MIPI/CSI-2 with D-PHY) interface on Toradex carrier boards, the differential trace impedance should indeed be 90Ω ±15%, and the single-ended impedance should be 50Ω ±15%. These values are specified to ensure optimal signal integrity for the high-frequency signals used by CSI-2, which can reach up to 500 MHz per data lane (1).

Using 100Ω differential trace impedance instead of the specified 90Ω may cause signal integrity issues due to impedance mismatch. This could lead to reflections, increased bit error rates, or even data loss, especially at faster data rates.

Key layout requirements for the CSI-2 interface include:

  • Differential impedance: 90Ω ±15%
  • Max intra-pair skew: <1ps (150µm)
  • Max trace length skew between clock and data lanes: <10ps (1.5mm)
  • Max trace length from the module connector: 200mm

To improve reliability, it is recommended to match your trace impedance as closely as possible to the Toradex-specified 90Ω differential. If redesign is an option, consider adjusting the traces accordingly.

Let me know if you have any more questions or need further guidance!

Best regards,
Toradex AI Assistant.

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Hi @forstnert

Do you have a reason to say that the design guide is wrong?
Could you please share more details about the issue you’re experiencing?

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Hi Allan,

Thanks for you reply.

Every other specification for CSI-2 I have seen specifies 100ohm impedance. I wanted to confirm that the layout guide’s specification of 90ohm was correct and why it differs from the standard.

My board uses a Toshiba TC358743XBG on convert HDMI to CSI-2 which is then input to a Verdin iMX8M Plus SoM (CSI_1). This interface usually works but the video freezes with about 30% of our SoMs. I am trying to figure out why this is happening.

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Hi @forstnert

I confirmed this with our hardware team.

It seems the 90Ω ±15% specification in the layout design guide is outdated.
This is valid only for the Colibri and Apalis families that included SoMs with chips from Nvidia.

And in the newer carrier board families,
which include the Verdin family, we route the MIPI signals with 100R.