MAX98357A on imx7s with simple-audio-card

@max.tx
Thank you, this was the solution. With the following dts file, the codec is now working as expected

/dts-v1/;
#include "imx7s-colibri.dtsi"
#include "imx7-colibri-eval-v3.dtsi"

/ {
	model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3";
	compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s",
		     "fsl,imx7s";

	//external Sound chip driver configuration
	codec_ext: max98357a@0 {
		compatible = "maxim,max98357a";
		#sound-dai-cells = <0>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "max98357a";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master_cpu>;
		simple-audio-card,frame-master = <&dailink_master_cpu>;
		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		simple-audio-card,codec {
			sound-dai = <&codec_ext>;
		};
		
		
		dailink_master_cpu: simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};
	};


};

&iomuxc {
	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio4
		     &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;

	pinctrl_sai2: sai2-grp {
		fsl,pins = <
			//Pin31
			MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x1f
			//Pin100
			MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x1f
			//Pin32
			MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
		>;
	};
	
 	pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
 		fsl,pins = <
 			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x14 /* DTR */
 		>;
	};
};

//disable the internal i2s
&sai1 {
	status = "disabled";
};

//enable the external i2s that we want to use
&sai2 {
	assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>, <&clks IMX7D_SAI2_ROOT_CLK>, <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	assigned-clock-rates = <0>, <36864000>, <589824000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};




//Remove all additional port pins from the uart and leave it with only RTS/CTS handshake
//Because we require one of these pins for SAII2
&uart1 {
	pinctrl-0 = <&pinctrl_uart1>;
};

//Remove pins 100 and 102 from the GPIO list, because we require it for the SAI2
&pinctrl_gpio1 {
	fsl,pins = <
		MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x14 /* SODIMM 77 */
		MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */
		MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
		MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14 /* SODIMM 93 */
		MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x14 /* SODIMM 95 */
		MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11	0x14 /* SODIMM 99 */
		MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x74 /* SODIMM 105 */
		MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x14 /* SODIMM 111 */
		MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x14 /* SODIMM 113 */
		MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x14 /* SODIMM 115 */
		MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x14 /* SODIMM 117 */
		MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x14 /* SODIMM 119 */
		MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x14 /* SODIMM 121 */
		MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x14 /* SODIMM 123 */
		MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14 /* SODIMM 125 */
		MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x14 /* SODIMM 127 */
		MX7D_PAD_UART3_RTS_B__GPIO4_IO6		0x14 /* SODIMM 131 */
		MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x14 /* SODIMM 133 */
		MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x14 /* SODIMM 169 */
		MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x14 /* SODIMM 24 */
		MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x14 /* SODIMM 102 */
		MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x14 /* SODIMM 104 */
		MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x14 /* SODIMM 110 */
		MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x14 /* SODIMM 112 */
		MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x14 /* SODIMM 114 */
		MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x14 /* SODIMM 116 */
		MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x14 /* SODIMM 118 */
		MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x14 /* SODIMM 120 */
		MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x14 /* SODIMM 122 */
		MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x14 /* SODIMM 124 */
		MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x14 /* SODIMM 126 */
		MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x14 /* SODIMM 128 */
		MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x14 /* SODIMM 130 */
		MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x14 /* SODIMM 132 */
		MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x14 /* SODIMM 134 */
		MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x14 /* SODIMM 150 */
		MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x14 /* SODIMM 152 */
		MX7D_PAD_SD2_CLK__GPIO5_IO12		0x14 /* SODIMM 184 */
		MX7D_PAD_SD2_CMD__GPIO5_IO13		0x14 /* SODIMM 186 */
	>;
};


&uart2 {
     status = "disabled";
};