Making PWM Pins (x10 18 & 19, SODIMM 15 & 16) available to the M7 on the mallow carrier board with IMX8MP

Technical Support
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1

Hello,

I’ve been working to configure the pin allocations for my project using the Verdin IMX8MP on the mallow carrier board. Currently, I’ve got the entire x19 header freed up for the M7 to use (it’s running an IO-heavy real-time hydraulics control software), and would also like to free up pins 18 and 19 on the x10 header (SODIMM 15 & 16) for use as PWMs 1 and 2.

Currently, I have the following nodes disabled in my device tree overlay:

// Making inputs available to the m7
&flexcan1 {
	status = "disabled";
};

&flexcan2 {
	status = "disabled";
};

&uart1 {
	status = "disabled";
};

&uart2 {
	status = "disabled";
};

&ecspi1 {
	status = "disabled";
};

// Making PWM available to the m7
&pwm1 {
	status = "disabled";
};

&pwm2 {
	status = "disabled";
};

Despite having the pwms disabled, I’m still not able to access those pins from the m7. Are there other nodes that I have to disable or configurations that I have to change? Is there a good way to free them up for the m7?

Output of tdx-info

Software summary
------------------------------------------------------------
Bootloader:               U-Boot
Kernel version:           5.15.177-6.8.2+git.5a6602cc6c32 #1-TorizonCore SMP PREEMPT Fri Mar 21 16:22:58 UTC 2025
Kernel command line:      root=LABEL=otaroot rootfstype=ext4 quiet logo.nologo vt.global_cursor_default=0 plymouth.ignore-serial-consoles splash fbcon=map:3 ostree=/ostree/boot.1/torizon/18efc6ca92e6b7703b53dbec9436fd49816f126e953c671819ad2e643a5fdbdd/0
Distro name:              NAME="TorizonCore"
Distro version:           VERSION_ID=6.8.2-build.30
Distro variant:           VARIANT="Docker"
Hostname:                 verdin-imx8mp-15230162
------------------------------------------------------------

Hardware info
------------------------------------------------------------
HW model:                 Toradex Verdin iMX8M Plus WB on Verdin Development Board
Toradex version:          0058 V1.1B
Serial number:            15230162
Processor arch:           aarch64
------------------------------------------------------------

Contents of /boot/ostree/torizon-*/dtb/overlays.txt

fdt_overlays=verdin-imx8mp_hdmi_overlay.dtbo verdin-imx8mp_spidev_overlay.dtbo cmc-pin-mux.dtbo cmc-shm.dtbo
  • the cmc-pin-mux file is our custom pin multiplexing overlay, and the cmc-shm file is our shared memory overlay. No pin conflicts exist between these overlays

Thanks,
Andrew

2

Hi, I’m the Toradex AI Assistant.

I might make mistakes. Our support team will step in if needed. If I answered your question, please tick the “Solution” checkbox. For follow-up questions to me, please use @ToradexAI in your post.

Did you like my answer? :+1: :-1:

Hello Andrew,

Thank you for your detailed question and for providing your configuration and system info.

Disabling the PWM peripheral nodes in your device tree overlay is an important first step, but to fully free SODIMM 15 & 16 (X10-18 & X10-19) for M7 access as PWM outputs, you also need to deconfigure their pin mux from Linux and ensure they are not assigned to any Linux subsystem. Let me walk you through what’s still needed:

1. Check Pin Multiplexing

Disabling peripherals releases the hardware, but the i.MX8M Plus pins are typically multiplexed (muxed) using the pinctrl subsystem. You need to make sure that the IOMUXC (pin mux) for these pins is not set by any Linux device tree node.

For SODIMM 15 (X10-18) and SODIMM 16 (X10-19), double-check in your base device tree (and overlays) that these pins are not pulled into any Linux pinctrl group.

How to Ensure Proper Pin Configuration

  • Explicitly set them as GPIO (input by default):
    Even if not used as GPIO by Linux, this removes their assignment from PWM or any other subsystem.
    Example node for SODIMM 15 (IOMUXC_GPIO1_IO08 for PWM1, sometimes called PWM1_OUT):

    &iomuxc {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_m7_pins>;

    pinctrl_m7_pins: m7-pins {
        // Assign SODIMM 15 and 16 to GPIO (or leave unused)
        fsl,pins = <
            IMX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x0 /* SODIMM 15, X10-18 */
            IMX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0 /* SODIMM 16, X10-19 */
        >;
    };
};
    • Use the correct IOMUXC names for your SoC revision.
    • This “unsticks” the pins from Linux (pwm, uart, can, etc.) and leaves them in a default state.

  • Alternatively, completely unconfigured (no assignment):
    The absence of assignment also works; the pins are left as they power up, available for the M7.

2. Check for Conflicts

Even with PWM disabled, these pins may be assigned to other peripherals in the device tree (UART, GPIO expander, etc.). Review which device tree nodes or overlays may reference these pins using the Pinout Designer Tool.

3. Update overlay and Compile

Your overlay should:

  • status = "disabled"; for PWM, UART, CAN, etc. on these pins
  • Remove the pins from any pinctrl groups assigned for Linux use
  • Add an (optional) “dummy” pinctrl group assigning them as GPIO, or just do not set their mux at all.

For overlay guidance:

4. Deploy Overlay and Reboot

Compile the overlay (e.g., using TorizonCore Builder) and deploy as needed:

5. Summary Checklist

  1. Disable Linux peripherals for those pins in the overlay (already done).
  2. Remove those pins from all Linux pinctrl groups.
  3. Optionally assign as GPIO or leave entirely unmuxed.
  4. Compile and deploy overlay, then reboot.

When that’s done, M7 firmware should be able to claim and use the pins for PWM, as Linux will neither control them nor interfere.

Let me know if you’d like a sample overlay skeleton or if you run into trouble.
Best regards,
Toradex AI Assistant.

3

In response to the ToradexAI suggestions,

After creating a pinctrl node using both the given template and the template given in the instructions for pinmuxing the imx8mp

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&cmc_gpios>;
	cmc_gpios: gpios {
		fsl,pins =
		<MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x0>,
		<MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x0>;
	};
};

and

&iomuxc {
	cmc_gpios: gpios {
		fsl,pins =
		<MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x0>,
		<MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x0>;
	};
};

When I applied the first one, my HDMI display stopped working, which indicates that it at least did something, if not what I intended it to. How else should I go about making the PWMs available to the M7? Are there other things I need to disable? Would it be possible to do so while still maintaining HDMI function?

4

Hey @aweaver,

I don’t believe the AI is correct here. From my knowledge disabling the PWM nodes should be enough not to have a resource conflict. I couldn’t find anywhere they are tied to other nodes for the imx8mp. Typical when there is a resource conflict, there is some sort of kernel panic on the linux side.

Are you able to boot into linux while you have this configuration? I will try and set something up myself to see if I get the same results.

5

Hi @eric.tx,

Thanks for getting back to me! It turns out that there was some confusion on my part as to the correct pin configuration & commands on the M7 side to manipulate the PWM. Since you confirmed that the PWM overlay on the linux side should work just fine, I was able to locate where my problem spots were on the M7 side and rectify them.

Thank you for your time!

Regards,
Andrew

6

Hey @aweaver,

Glad you were able to pin down the correction and I could help!

-Eric

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