I’m in design- and layout-phase in project which uses Verdin iMX8M Plus SOM. For a legacy display, I need to use LVDS and translate it to Parallel RGB with the chip SN75LVDS82 from TI.
Now, I’m a little bit confused about the signal assignment on the SOM. As far as I know, the normal pin assignment on LVDS is Data0, Data1, Data2, Clk, Data3 - on SN75LVDS82 (and also other LVDS chips) is the assignment like this…
On Verdin iMX8M Plus SOM, the pin assignment is Clk, Data0, Data1, Data2 Data3 what results in crossed diff.-signals when I route from SOM to SN75LVDS82.
Now my question: Is the pin assignment on SOM really like in datasheet described or is it eventually an errata in datasheet?
Could anybody confirm the pin-assignment in datasheet of LVDS0 like following:
Pin90 → LVDS0_CLK_P
Pin88 → LVDS0_CLK_N
Pin96 → LVDS0_D0_P
Pin94 → LVDS0_D0_N
Pin102 → LVDS0_D1_P
Pin100 → LVDS0_D1_N
Pin108 → LVDS0_D2_P
Pin106 → LVDS0_D2_N
Pin114 → LVDS0_D3_P
Pin112 → LVDS0_D3_N
Because I’m already in the layout-phase, it were very helpful to get a confirmation resp. an answer as son as possible.