LVDS display on native LVDS0 port on mx8mp-verdin

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LVDS Configuration for Verdin iMX8M Plus

Based on the Verdin iMX8M Plus datasheet, the module features one LVDS interface that can be configured for single or dual-channel with 18 and 24-bit color depth(1). The LVDS signals are on module-specific pins and are not guaranteed to be compatible with other Verdin modules(1).

LVDS Interface Specifications

The Verdin iMX8M Plus LVDS interface supports:

  • Single channel: resolutions up to 1366x768 pixels @60fps (80MHz pixel clock maximum)(2)
  • Dual-channel: resolutions up to 1920x1080 @60fps (160MHz pixel clock maximum)(2)
  • Both 18-bit and 24-bit color mappings including JEIDA and VESA formats(2)

LVDS Signal Pinout

The LVDS signals are mapped to the following X1 connector pins(2):

Channel 0 (Single Channel/Odd pixels):

  • Clock: MSP_1/MSP_2 (LVDS0_CLK_N/P)
  • Data Lane 0: MSP_4/MSP_5 (LVDS0_D0_N/P)
  • Data Lane 1: MSP_6/MSP_7 (LVDS0_D1_N/P)
  • Data Lane 2: MSP_9/MSP_10 (LVDS0_D2_N/P)
  • Data Lane 3: MSP_11/MSP_12 (LVDS0_D3_N/P) - unused for 18-bit

Channel 1 (Dual Channel/Even pixels):

  • Clock: MSP_14/MSP_15 (LVDS1_CLK_N/P)
  • Data Lanes: MSP_16 through MSP_25 for the four differential pairs

Device Tree Configuration Approach

For native LVDS display integration, you’ll need to create a device tree overlay that configures the LVDS interface properly(3). The configuration should include:

  1. LVDS Channel Configuration: Set the fsl,data-mapping and fsl,data-width properties to match your display requirements(4)

  2. Panel Timing Definition: Define the panel timing parameters including clock frequency, active resolution, sync lengths, and porch values(4)

  3. Color Mapping: Configure the appropriate color mapping (JEIDA or VESA format) based on your display specifications(2)

Troubleshooting Steps

Since you’re not seeing any pixel clock activity:

  1. Verify Device Tree Loading: Ensure your overlay is properly loaded and the LVDS interface is enabled in the device tree
  2. Check Display Controller Binding: Confirm that the display controller (LCDIF) is properly bound to the LVDS interface
  3. Validate Timing Parameters: Ensure all timing parameters are correctly calculated and within the supported ranges

Alternative: Verdin AM62 Consideration

If you have a Verdin AM62 module available, it also supports native LVDS through the Open LVDS Display Interface (OLDI)(5). The AM62 can support resolutions up to 1920x1080p at 60fps with a 165MHz pixel clock maximum(5), and the LVDS interface is similarly classified as module-specific(5).

The AM62 LVDS implementation provides 8 data lanes split into 2 channels, which might offer more flexibility for your debugging efforts(5).

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