LVDS display on native LVDS0 port on mx8mp-verdin

Technical Support
1

Hello everyone,

I’ve been fighting to get my custom display-breakout board working for the past two days (TI 90DS384xx with a low resolution 4,3” RGB display attached).

I got my devicetree to the point, that a framebuffer is created, but i can’t see any output on the display. I found out about the LVDS pixel-clock issue yesterday (mx8mp-lbd.c in the kernel) - so i don’t expect the display to work without a kernel patch.

So I tried to at least have a look at the signals with a scope, but i can’t see any activity on the pixel-clock at all. It’s only a logic-analyzer that can sample up to 50MSPS, so I would clearly only see noise on activity - but I only see a flat signal.

Also fbset reports a display of the defined size, but with all 0 timings.

Can you support me with a known good device-tree file, which will output “something” on the native LVDS0 port of the mx8mp-verdin modul? I can’t even debug my electronics at this point.

I’ve got a verdin-evk carrier board around, but no mezzanize connector - also an addition AM62 modul, if that would help.

Best regards!

2

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LVDS Configuration for Verdin iMX8M Plus

Based on the Verdin iMX8M Plus datasheet, the module features one LVDS interface that can be configured for single or dual-channel with 18 and 24-bit color depth(1). The LVDS signals are on module-specific pins and are not guaranteed to be compatible with other Verdin modules(1).

LVDS Interface Specifications

The Verdin iMX8M Plus LVDS interface supports:

  • Single channel: resolutions up to 1366x768 pixels @60fps (80MHz pixel clock maximum)(2)
  • Dual-channel: resolutions up to 1920x1080 @60fps (160MHz pixel clock maximum)(2)
  • Both 18-bit and 24-bit color mappings including JEIDA and VESA formats(2)

LVDS Signal Pinout

The LVDS signals are mapped to the following X1 connector pins(2):

Channel 0 (Single Channel/Odd pixels):

  • Clock: MSP_1/MSP_2 (LVDS0_CLK_N/P)
  • Data Lane 0: MSP_4/MSP_5 (LVDS0_D0_N/P)
  • Data Lane 1: MSP_6/MSP_7 (LVDS0_D1_N/P)
  • Data Lane 2: MSP_9/MSP_10 (LVDS0_D2_N/P)
  • Data Lane 3: MSP_11/MSP_12 (LVDS0_D3_N/P) - unused for 18-bit

Channel 1 (Dual Channel/Even pixels):

  • Clock: MSP_14/MSP_15 (LVDS1_CLK_N/P)
  • Data Lanes: MSP_16 through MSP_25 for the four differential pairs

Device Tree Configuration Approach

For native LVDS display integration, you’ll need to create a device tree overlay that configures the LVDS interface properly(3). The configuration should include:

  1. LVDS Channel Configuration: Set the fsl,data-mapping and fsl,data-width properties to match your display requirements(4)

  2. Panel Timing Definition: Define the panel timing parameters including clock frequency, active resolution, sync lengths, and porch values(4)

  3. Color Mapping: Configure the appropriate color mapping (JEIDA or VESA format) based on your display specifications(2)

Troubleshooting Steps

Since you’re not seeing any pixel clock activity:

  1. Verify Device Tree Loading: Ensure your overlay is properly loaded and the LVDS interface is enabled in the device tree
  2. Check Display Controller Binding: Confirm that the display controller (LCDIF) is properly bound to the LVDS interface
  3. Validate Timing Parameters: Ensure all timing parameters are correctly calculated and within the supported ranges

Alternative: Verdin AM62 Consideration

If you have a Verdin AM62 module available, it also supports native LVDS through the Open LVDS Display Interface (OLDI)(5). The AM62 can support resolutions up to 1920x1080p at 60fps with a 165MHz pixel clock maximum(5), and the LVDS interface is similarly classified as module-specific(5).

The AM62 LVDS implementation provides 8 data lanes split into 2 channels, which might offer more flexibility for your debugging efforts(5).

Best regards, Toradex AI Assistant.

3

Hello @seeligerec,

There are a few things that you need to be mindful in you current setup:

  • Checking the value of differential signals such as LVDS with a Logic Analyzer is not ideal. You may completely miss the signal. A differential probe would be more adequate, even if you are just looking for noise to ensure something is happening on that signal.
  • The DS90CF384AQ-Q1 should be able to do the deserialization you need, however, as you are not using a paired FPD Link 1 transmitter, special care must be taken with the bit mapping that goes to the display, so it matches either the JEIDA or VESA pixel mapping which can be transmitted by the Verdin iMX8MP via LVDS.

If you want a device tree overlay that has LVDS working, we have them available on our device-tree-overlays repository.
For example:

I would recommend that you start from one of the overlays we provide and then customize it to the needs of your display.
You are correct when saying that a kernel patch will be needed to achieve a lower pixel clock with the Verdin iMX8MP.

Best Regards,
Bruno