Lcd pixel clock polarity


We want to use the named LCD together with Apalis. The problem is, for this LCD we need the pixel clock to operate on falling edge. We already checked with a hardware inverter that it works fine with the changed pixel clock polarity.

But we would like to leave out this inverter and change the pixel clock polarity by software. It seems this is possible with the iMX6, but we haven’t succeeded so far to change it.

With fbset we could change the pixel clock frequency but there is no option for the polarity (at least we didn’t found one).

root@apalis-imx6:/# fbset -t 111111 2 2 2 2 41 10
root@apalis-imx6:/# fbset
mode "480x272-60"
		# D: 9.000 MHz, H: 17.143 kHz, V: 59.940 Hz
		geometry 480 272 480 544 16
		timings 111111 2 2 2 2 41 10
		accel false
		rgba 5/11,6/5,5/0,0/0

The output frequency and the screen refresh rate are like expected.
link text
We also tried to change U-Boot vidargs but also without success.

setenv vidargs 'video=mxcfb0:dev=lcd,480x272M@60,if=RGB24,pixclockpol:0, video=mxcfb1:off'

Is it possible that the syntax is not correct?

We also tried to change the device tree with the adopted settings from fbset, but that didn’t work.
Here is snippet and the full device-tree is attached:
mxcfb1: fb@0 {
compatible = “fsl,mxc_sdc_fb”;
disp_dev = “lcd”;
interface_pix_fmt = “RGB24”;
default_bpp = <16>;
int_clk = <0>;link text
late_init = <0>;
status = “disabled”;
&lcd {
display = <&display0>;
status = “disabled”;

     display0: display {
         bits-per-pixel = <24>;
         bus-width = <24>;
         display-timings {
             native-mode = <&timing_lcd>;
             /* LCD Timing, LCD 480x272 4'3" */
	    timing_lcd: 480x272 {
                 clock-frequency = <9000000>;
                 hactive = <480>;
                 vactive = <272>;
                 hback-porch = <2>;
                 hfront-porch = <2>;
                 vback-porch = <2>;
                 vfront-porch = <2>;
                 hsync-len = <41>;
                 vsync-len = <10>;
                 de-active = <1>;
                 hsync-active = <0>;
                 vsync-active = <0>;
                 pixelclk-active = <0>;

Thank you in advance,

Unfortunately pixelclock property works only on tegra based modules. Vidargs have priority over data in the device tree, if no resolution information is given in vidargs (setenv vidargs video=mxcfb0:dev=lcd) config from the device tree should be used (you’ll also need to change status to “okay” for lcd devicetree node in both locations).

@dominik.tx Does this answer also apply to Colibri iMX7? I would also like to invert the clock polarity on my CPU module.

Hi @michaelg. Yes, you need to the invert the clock polarity in device-tree?

Best regards,

@jaski.tx Can you help me here with my followup question?

Which follow up question?