LCD flickering on i.MX7D Colibri after kernel upgrade

Technical Support
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8

Great! Now that you’ve confirmed the pixel clock mismatch, let’s address this issue. Based on the available documentation, there are several approaches to resolve pixel clock precision problems in Linux 6.x kernels.

Clock Configuration Solutions

1. Dynamic Clock Rate Configuration

Based on community experience with similar pixel clock issues, newer kernels support dynamic PLL configuration that can provide more precise clock frequencies(1). The key is to enable the pixel clock to reconfigure its parent PLL to achieve the exact frequency needed(1).

For your i.MX7D setup, you can try modifying your device tree to allow dynamic clock rate adjustment:

&lcdif {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_lcdif_dat
                 &pinctrl_lcdif_ctrl
                 &pinctrl_lcdif_dat_24>;
    
    /* Allow dynamic PLL reconfiguration */
    assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>,
                      <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
    assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
    assigned-clock-rates = <0>, <51200000>;
    
    lcd-supply = <&reg_3v3>;
    
    port {
        display_out: endpoint {
            remote-endpoint = <&panel_in>;
        };
    };
};

(1)

2. Alternative Clock Frequencies

If the exact 51.2 MHz cannot be achieved, try frequencies that the video PLL can generate more accurately. Common frequencies that work well with i.MX7D video PLL include:

  • 50.0 MHz - Often achievable with better precision
  • 49.5 MHz - Alternative that may provide stable timing
  • 52.0 MHz - Slightly higher frequency option

Update your panel timing accordingly:

panel-timing {
    clock-frequency = <50000000>;  /* Try 50 MHz instead */
    hactive = <1024>;
    vactive = <600>;
    /* Adjust porch values proportionally if needed */
    hfront-porch = <160>;
    hback-porch = <160>;
    hsync-len = <20>;
    vfront-porch = <12>;
    vback-porch = <23>;
    vsync-len = <3>;
    de-active = <1>;
    hsync-active = <0>;
    vsync-active = <0>;
    pixelclk-active = <1>;
};

3. Video PLL Configuration Verification

The video PLL on i.MX7D has specific multiplication factors that determine which frequencies can be generated precisely(1). The issue often occurs when the requested frequency doesn’t align well with the PLL’s available output frequencies(1).

4. Kernel Clock Framework Debugging

To verify the actual clock being generated, you can check the kernel clock framework output:

# Check actual clock rates
cat /sys/kernel/debug/clk/clk_summary | grep -i lcdif

This will show you the actual frequencies being generated versus what you requested.

5. Device Tree Compilation and Deployment

After making changes to your device tree, ensure proper compilation(2):

# Compile your custom device tree
make DTC_FLAGS="-@" imx7d-colibri-eval-v3-custom.dtb

(2)

6. Alternative Approach: Clock Source Selection

If the video PLL cannot provide the exact frequency needed, consider using an alternative clock source that might offer better precision for your specific frequency requirement.

Recommended Testing Sequence

  1. Start with 50 MHz: This frequency is often more achievable with the video PLL
  2. Verify actual vs. requested frequency: Use the clock debugging tools
  3. Gradually adjust: If 50 MHz works, try frequencies closer to your target
  4. Monitor display stability: Test each configuration thoroughly

The pixel clock precision issue you’re experiencing is a known challenge when upgrading to newer kernels, as they have stricter timing validation(1). The solution typically involves finding a frequency that the video PLL can generate accurately rather than forcing an imprecise frequency.

Best regards,
Toradex AI Assistant.

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