I would like to use the JTAG interface of the Colibri Evaluation Board with Colibri iMX6DL COM attached. The debug interface on the evaluation board seems to be compatible with our Segger J-Link Plus JTAG debugger.
However, during the J-Link adapter initialization the J-Link adapter cannot connect to the board with the tools provided by Segger. We tried it with the following settings for connection:
Cortex-A9 arm core
Auto clock settings
We installed the latest Toradex Embedded Linux on the COM module.
It would be nice to have a working OpenOCD configuration file to use the JTAG interface with this setup.
Could you send a working OpenOCD configuration or could you provide any information regarding the JTAG usage in our setup?
The Colibri iMX6DL supports JTAG access in two different modes:
Boundary Scan
Debug access
By default the hardware is configured for Boundary Scan operation. To switch to the JTAG Debug access, SODIMM pin 180 needs to be pulled to GND. On the Evalboard V3.2 this can be done on the white extension connector X3: short the pins C12 (DATA_31) and B2 (GND).
There’s also an assembly option on the module itself to switch the JTAG mode permanently.
An potential error are also the spring-loaded Pogo pins underneath the module, which are used to connect the JTAG signals. Make sure the module is inserted properly into the socket. If the socket is worn-out, it might help to put some weight onto the module, in order to push it properly onto the pogo pins.
Software
Instead of selecting the generic Cortex-A9 core in the SEGGER software, choose the MCIMX6U7 device. This way, SEGGER takes care of the proper initialization of the whole system.
Here is a log of the J-Link Commander V6.40, running under Windows 10:
I’d like to get debug mode JTAG access to the same iMX6 module, but on an Aster Carrier Board.
As I see from the documentation, the mentioned pin 180 is not exposed on the Aster board so pulling it to GND through a connector is not an option.
What is your advice in such case, how could the module turned to JTAG debug mode?
Thank you for your response.
I’d like to use the Aster board, so the preferred solution would be to make the pull down via soldering. However I did not find any related information on the given pads.
How can I identify this or where can I found the corresponding information?
For the location of the pad: On the top side, where the SOC is placed, you have to look above of upper right corner (SODIMM Pins showing down). There is a Testpoint. Near to this is the place for R66. There you need to solder a resistor of 1k to Pull down the Pin 180 to GND. I have also attached a picture .
**Note that this Soldering will be only for Testing and Debugging and should not be used in Production. **
