Is there any sample out using GPIO interrupts, SPI using DMA and UART using DMA on i.MX7 under WEC 2013?

Hi,
I am looking for help for a jump start into i.MX7 running WEC8, so is there any sample available using SPI and UART with DMA support and generating Interrupts when an GPIO changes?

Thanks for helping

With best regards

Gerhard

Dear @Gerhard

There are some samples which should help you included in the Toradex CE Libraries package.

SPI

Look at the Spi_Demo in the library package. DMA mode is not supported.

GPIO Interrupt

Look at the Int_Demo in the library package

UART

By default, the UARTs are operating without DMA. You can enable the DMA mode through a registry setting. Please refer to the following article:

Regards, Andy

Hi Andy,

hmmm. Looked at Spi_Demo.
There were 20 bytes for transfer, ok. The function itself is a synchron function, used within a task will be ok. But, did the hardware generate 20 interrupts which were handled by the ReadWrite function, which ends up in a high processor burden, or is DMA used for this job to free the processor?

As the SPI interface is a very fast interface, generating an interrupt on each transferred byte isn’t that good idea (for my opinion).

My application uses SPI (master on Colibri side) to get 630 byte frames from another system, total byte count at the end of the whole transfer is several mega-bytes. The other system using a queueing system to decouple the two systems time domains, but as the working memory is limited, the response time of the Colibri can’t get too long.

Currently I use a module based on a single kernel Atmel processor running at 500Mhz, which does the job, but this module is discontinued as the company which produces this module is gone.

Now I hope that the Colibri i.MX7 (choosen for its low power consumption) will do the job.

With best regards

Gerhard

Hi Andy,

I get the IRIS Carrier Board V1.1 and I guess, the SPI interface is routed to some pins of the 40p extension connector X16:

1145-spi-on-x16.jpg

The signal SSPFRM is the signal normally called nCSx (Chip Select)?

And I guess it is nCS0?

I am right? Is there some detailed information, how the signals of this pins should be interpreted using the SPI interface of the COLIBRI i.MX7 duo on an IRIS V1.1 board?

Thanks a lot.

With best regards

Dear @Gerhard

The interpretation of the signals is not fully straight-forward, because each signal is going through the chain SoC → Colibri → Iris

  • In the Iris Carrier Board Datasheet (or the Iris schematics) you already found the information, that the SPI pins are routed to the SODIMM pins 86, 88, 90 and 22, your guess was correct.
  • In the Colibri iMX7 datasheet, section 5.11 explains, that the SODIMM pins 86, 88, 90 and 92 connected to the iMX7’s ecspi 3 controller.

In our Toradex CE libraries we use the convention that the port “SPI1” always controls the SPI port on SODIMM pins 86, 88, 90 and 92, so by default you don’t need to worry about this mapping.

Regards, Andy

Dear @Gerhard

To keep the overview over different posts, I moved this query to a new question:

Regards, Andy