On Toradex web page, I saw some examples about interrupt usage on SoM modules but all of them are given for WinCE. We are intended to use Verdin iMX8M-Plus with custom yocto build (linux) and we need an interrupt input pin for one of the peripheral that will be connected to the SoM.
Is it possible to find an example about how to use interrupt pins on a Verdin iMX8M-Plus with Linux OS? The example would be beneficial to identify which pins to use, how many pins available to generate interrupt in the kernel, what would be the latency, what would be the possible speed can be managed by the Verdin module, which CPU core manages the IRQ and what if we have multiple interrupts etc.
Your helps are highly appreciated.
Hi @Fide ,
Thanks for contacting Toradex.
Would it be possible that you share some more insight in your project and what you’re trying to achieve?
Are the interrupt pins you talk about, GPIO pins?
The legacy way of doing it can be found in this article about GPIO sysfs
With newer modules you can use the following commands on CLI to evaluate the pins.
About some of your other questions.
The latency is variable, it depends in which mode the CPU is at that moment, how you configure the interrupts and for example the kernel configuration. This is why it would help us if you share more about your project.
On our github you can also find an example in c. You can crosscompile it to fit your module.
There is no way to know, which CPU manages this, because the scheduler assigns them accordingly.
This is quite nice repo that I wasn’t aware of before, thank you for sharing.
I went through the example code that you referred and gpiod_line_request_rising_edge_events() and gpiod_line_event_wait() functions sound like polling the ports instead of real interrupt generation to the CPU. I will test them on a Dahlia board with iMX8M-Plus but I believed that they can work with arbitrary GPIO since they don’t really generate IRQ to the CPU.
Our needs is a little bit different. Imagine that we have a 32 bits ADC which has a DR (data ready pin) and connected to the SoM through a SPI bus. (SoM master, ADC is slave). Once configured properly, ADC asserts DR pin periodically (at ADC’s sample rate). The SoM should catch the DR pin and initiate SPI communication and read all samples through DMA. This operation should be done without interleaving the CPU.
Therefor I need to know which pin is capable of generating real interrupt request to the CPU and also can trigger a DMA operation for a SPI communication.
Your directions are highly valuable for us.
Hi @Fide !
Thanks for sharing your use case.
It seems that you want an ADC solution and this would be better to implement in a kernel driver. All the functionality associated with the DMA and interrupts would be implemented inside the kernel driver.
Based on this, maybe the best way to go is to find an ADC chip that already has Linux Kernel support, like the TLA2024, that is featured on Verdin iMX8M Plus.
It is possible that other ADC chips also already have kernel support, so you can research if some of them meet your specific requirements.