iMX8QM pcie0 2x lane width

Hello everyone.

I have an issue where I can’t establish PCIe x2 link between SoM and device, but x1 link works.

I have custom carrier board with Apalis iMX8QM v1.1B SoM. The SoM is running a custom OS, based on Boot2Qt, with kernel version 4.14. The carrier board contains Marvells AQVC-107 10G ethernet controller. The SoM interfaces with ethernet controller via PCIExpress link on PCIE0 controller (&pciea node in device tree).

In device tree, when the hsio-cfg in pciea node is set to PCIEAX1PCIEBX1SATA, the PCIe link is established sucessfully with AQVC107. But when I try with PCIEAX2PCIEBX1, the device doesn’t show up in lspci output.

Could you help me find out why is this happening? I’ve attached lspci -vv output for the first case when the link is established with PCIe x1 and the dmesg output for the second case when the device is not visible on PCIe x2

Additional info: pcieb (PCIE1) and sata nodes in device tree are disabled.


Martin Lovrić,
Software Engineer

The attachment upload and code formatting is not working, so if you need these outputs please provide me an e-mail and I’ll send you.

Hi @Martin_Lovric,

There is nothing attached.

Could you provide the logs and outputs you’ve commented on?

Best regards,
André Curvello

@andrecurvello.tx is the attachment visible in this comment?

Hello Martin,

PCIe needs special care on the PCB layout side.
Can you provide you schematic for a review? In general, it is always recommended to let us do a schematic and design review to reduce design spins on your side.
please also try to operate the Marvells AQVC-107 10G ethernet controller on an IXORA board if you have a mini PCIe card available.

Best Regrads,
Matthias Gohlke

Hi Martin

Could you also share the U-boot output? Thanks.

Hello @matthias.tx
We have communication over one lane and the second lane is routed in the same way so I believe HW shouldn’t be an issues, unfortunately we can’t run AQVC107 on IXORA board since it is integrated into our carrier board.

Here are the schematics of AQVC107 chip, if you need more, let me know.
AQVC107 line-side

Apalis side

sorry for the delay, here is the output from U-boot, let me know if you’d prefere it in txt file rather

alt text

Hi @Martin_Lovric

The U-boot output was not properly uploaded. Could you share in text format? Thanks.

Hi, I seen you duplicate support email and I answer you there.

Best Regards,

Matthias Gohlke

Hello everyone,

I was on vacation so I wasn’t able to reply sooner.

My colleague found out that the num-lanes property in pciea node in the device tree was set to 1, after changing it to 2 and setting hsio-cfg to PCIEAX2PCIEBX1 he succeeded to establish PCIe link with the AQVC107.


Hi @Martin_Lovric

Perfect that the issue is solved. Thanks for the feedback.

Best regards,