IMX8QM eth2 KSZ9131RNXI never up

[78rbe]

Hi,

On the Apalis IMX8QM with a custom board, the interface is never up.

Here the dts :

&fec2 {
pinctrl-names = “default”, “sleep”;
pinctrl-0 = <&pinctrl_fec2>;
pinctrl-1 = <&pinctrl_fec2_sleep>;

fsl,magic-packet;
fsl,mii-exclusive;

phy-supply = <&reg_ext_rgmii>;
phy-handle = <&ethphy1>;
    phy-mode = "rgmii-id";

status = "okay";

mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy1: ethernet-phy@7 {
		compatible = "ethernet-phy-ieee802.3-c22";
		interrupt-parent = <&lsio_gpio2>;
		interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
		micrel,led-mode = <0>;

		reset-assert-us = <10000>;
		reset-deassert-us = <50000>;
		reset-gpios = <&lsio_gpio2 23 GPIO_ACTIVE_LOW>;
		reset-names = "phy-reset";

		reg = <7>;
	};
};
};

pinctrl_fec2: fec2grp {
fsl,pins = <
IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020
IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000060
IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020
IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020
IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020
IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020
IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020
IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020
IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020
IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020
IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020
IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020
IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020
IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020
IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M 0x06000020
IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x04000060

;
};

pinctrl_fec2_sleep: fec2-sleepgrp {
fsl,pins = <
IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0

IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18		0x04000040
IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17		0x04000040
IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11	0x04000040
IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10		0x04000040
IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12		0x04000040
IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13		0x04000040
IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14		0x04000040
IMX8QM_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15		0x04000040
IMX8QM_ENET1_RGMII_RXC_LSIO_GPIO6_IO16		0x04000040
IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17	0x04000040
IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18		0x04000040
IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19		0x04000040
IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20		0x04000040
IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21		0x04000040
/* IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16	0x04000040 */
/* not wired on ECU */
/* IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11		0x06000020 */
IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x04000040
>;

};

[ 7.406371] Microchip KSZ9131 Gigabit PHY 5b050000.ethernet-2:07: attached PHY driver (mii_bus:phy_addr=5b050000.ethernet-2:07, irq=280)

# ethtool eth1

Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Port: Twisted Pair
PHYAD: 7
Transceiver: external
Auto-negotiation: on
MDI-X: Unknown
Supports Wake-on: g
Wake-on: d
Link detected: no

I have tried to force the phy at 100M, without success

# ethtool -s eth1 speed 100 duplex full autoneg off

The interface never up even with this command.

3: eth1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq qlen 1000
link/ether 00:14:2d:7d:ef:a2 brd ff:ff:ff:ff:ff:ff
inet 192.168.1.1/24 scope global eth1
valid_lft forever preferred_lft forever

On the PCB, the KSZ9131 is routed in the 10/100 configuration. Only the ports A and B in connected to the transceiver.
A crystal @25MHz is connected to on the XI/XO pins and it works great.

I see the clock on the mdc pin when I set up the interface and I see something trying to discuss with the address 7. My ksz if configured with the address 7.

The reset pin is high.

Any idea ?

[ToradexAI]

Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

---

I’d be glad to help troubleshoot your Ethernet issue! To provide the most accurate guidance, could you please specify which OS and version you are running? You can get this information by running the tdx-info command on your device.

For comprehensive hardware and software details, please refer to the tdx-info documentation.

Initial Analysis

Based on your configuration, I can see several potential issues that commonly cause Ethernet interfaces to fail on Toradex modules:

PHY Mode Configuration

Your device tree shows phy-mode = "rgmii-id" but you mention the KSZ9131 is configured for 10/100 operation with only ports A and B connected (1). For 10/100 operation, you should typically use phy-mode = "rmii" instead of RGMII.

Clock Configuration Issues

The KSZ9131 with a 25MHz crystal suggests it’s generating its own reference clock. You may need to verify the clock configuration in your device tree matches your hardware setup (1).

Common Troubleshooting Steps

Based on similar issues reported in the community (2)(3), here are key areas to investigate:

1. Regulator Configuration: Ensure your reg_ext_rgmii regulator is properly configured and not causing probe deferrals
2. Reset Timing: Your reset timing looks correct, but verify the reset GPIO is functioning properly
3. PHY Address: Confirm the PHY is actually responding at address 7 on the MDIO bus

Device Tree Verification

Since you can see MDIO communication attempting to reach address 7, the basic communication path appears functional. However, the mismatch between RGMII configuration and 10/100 hardware setup is likely the root cause.

Once you provide the OS version information, I can give you more specific guidance tailored to your platform.

Best regards, Toradex AI Assistant.

---

Did you like my answer?

If I answered your question, please tick the “Solution” checkbox.

For follow-up questions to me, please use @ToradexAI in your post.

[bruno.tx]

Hello @78rbe,

When enabling a Phy, there are many things that can go wrong.

In this case, I think I know what the problem is.
You mentioned:

@78rbe

On the PCB, the KSZ9131 is routed in the 10/100 configuration. Only the ports A and B in connected to the transceiver.

From this, I understand that you do not have the full RGMII wired to the Phy, meaning that it will need to operate in RMII mode.
If that is the case, you need to make sure that your device tree configuration reflects that and that the reference clock is correct for this mode of operation.
Currently, you have phy-mode = "rgmii-id"; which configures the Phy for RGMII.
Generally, even if just using 100 Mb, wiring the full RGMII and then limiting the speed in the configuration is a better approach if both SoC and Phy support it.

Regardless, I would also recommend that you double-check a few things in your design:

• Phy strapping: this can set the mode of the Phy as well as the address and speed.
• Rx and Tx connections, most Phys require a direct Rx ↔ Rx and Tx ↔ Tx connection, so please double check this is correct for your phy

Best Regards,
Bruno

[78rbe]

Thank you your response !

As you can see, I use the full rgmii on the design.

I tested the rmii mode without success.

Thanks for your help

[bruno.tx]

Hello @78rbe,

Thanks for the clarification and additional information.
RGMII should be the correct configuration then.

I see the following issue in the design:

• MDC and MDIO are connected directly from the SoM to the Phy.

These signals are 3.3 V on the SoM, so they would need a level shifter to work with the 1.8V on the Phy.
This is something you can test with an external level shifter, by removing R241 and R242.

There is another issue in your device tree, the RGMII signals have a configurable voltage on the Apalis iMX8.
This is done via the configuration of the reg_ext_rgmii regulator.
For your use, it looks like 1.8V is needed, but the default configuration is 3.3V: Making sure you're not a bot!

Best Regards,
Bruno

[78rbe]

Yes I already taken a look on reg_ext_rgmii and its configured as follow :

reg_ext_rgmii: regulator-ext-rgmii {
	compatible = "regulator-fixed";
	power-domains = <&pd IMX_SC_R_BOARD_R2>;
	regulator-max-microvolt = <1800000>;
	regulator-min-microvolt = <1800000>;
	regulator-name = "VDD_EXT_RGMII (LDO1)";

	regulator-state-mem {
		regulator-off-in-suspend;
	};
};

I will test with a level shifter and I’ll let you know if it works.

But I use the design from your Verdin Development Board schematics where the MDIO and MCD are directly connected to the imx.

[bruno.tx]

Hi @78rbe,

Understood, I will await your results.

@78rbe

But I use the design from your Verdin Development Board schematics where the MDIO and MCD are directly connected to the imx.

The Verdin SoM Family has a default I/O voltage of 1.8V, so a level shifter is not needed in that case.
The Apalis iMX8 has level-shifters for its internal MDIO/MDC lines used for the onboard phy, exactly because the power group is fed with 3.3V and the phy requires 1.8V.

Best Regards,
Bruno