I wonder what is the maximum length mismatch of the differential lines on LVDS interface?
I am talking about PCB layout design.
Let’s consider full HD as target.
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Hi @CONSTRUCTOR ,
Please let us know if you need further help.
Thanks @alex.tx for looking this up 
Best Regards
Kevin
Hi Kevin
This already helps to solve part of the problem. In the document is written, that the tolerance for maximum Bitrate is 150um ==1ps.
When we calculate the sampling requirements (1/(80MHz2(clock cycles) 7(bits per clock)*10(sample safety margin)) we land at 89ps. Can you help me why the tolerance is as low as 1ps?
We are using Verdim iMX8M Plus Modules.
Hi @CONSTRUCTOR
The 1ps is the intra-pair skew. This means the difference between the positive and negative components of the differential pair signals. It is very important to keep these skews as small as possible, as it has an effect on the crossing point of the differential signal. It also has an effect on the EMI cancellation efficiency a differential signal has. This is the reason why you should keep the skew below 1ps even in longer segments of the transmission line.
Your calculations reflect the skew between the clock pair and the data pairs. In our guide, we propose 3.5ps. You might further relax this requirement in your design. However, I would not recommend going with the full 89ps. The whole display path has further signal mismatching which could cause issues in the end. For example, if there is a bridge from LVDS to parallel RGB, you will also have some skew between the RGB signals. There is also some skew on the module side for the LVDS signals. This is the reason why we propose to match the signals a bit better than just by a tenth of the clock cycle.
Hi @CONSTRUCTOR ,
Hope your doing great!
Were the hints from Peter helpful for you?
Best Regards
Kevin
Hi Kevin
Thank you for asking. Yes, it helped us a lot.
Thank Peter and you for the great support.
Best Regards
Daniel
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