Imx8mp dsi-to-lvds: issue with display configuration

Hello,

We are encountering issues while setting up the Verdin Dev Board v1.1f (Verdin imx8mp) with the RVT50HQLNWC00-B display (Riverdi) through the Toradex DSI-to-LVDS Adapter (rev 1.1).

The display works correctly on our custom board, where it is connected directly to the LVDS output of the imx8mp (after applying kernel driver changes outlined here). These changes require the use of Yocto, but we would like to avoid it in production in order to maintain full compatibility with the Torizon environment.

We have created a device tree overlay for the RVT50HQLNWC00-B 5-inch display based on files provided by Toradex: display-lt170410_sn65dsi84_overlay.dtsi and verdin-imx8mp_dsi-to-lvds_panel-cap-touch-10inch-lvds_overlay.dts.

  • display-rvt50hqlnwc00b_sn65dsi84_overlay.dtsi:
// Verdin DSI to LVDS Adapter with connected RVT50HQLNWC00-B display (5 inch) with a
// resolution of 800x480 pixel.

&lvds_ti_sn65dsi84 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@2 {
			reg = <2>;

			lvds_out_panel: endpoint {
				remote-endpoint = <&panel_in_lvds>;
			};
		};
	};
};

&panel_lvds {
	compatible = "panel-lvds";
	backlight = <&backlight>;
	data-mapping = "vesa-24"; // jeida-24
	height-mm = <108>;
	width-mm = <65>;
	status = "okay";

	panel-timing {
		clock-frequency = <25000000>;
		de-active = <1>;
		hactive = <800>;
		hback-porch = <48>;
		hfront-porch = <48>;
		hsync-len = <8>;
		pixelclk-active = <1>; /* positive edge */
		vactive = <480>;
		vback-porch = <12>;
		vfront-porch = <12>;
		vsync-len = <8>;
	};

	port {
		panel_in_lvds: endpoint {
			remote-endpoint = <&lvds_out_panel>;
		};
	};
};
  • verdin-imx8mp_dsi-to-lvds_panel-cap-touch-5inch-lvds_overlay.dts:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2020-2022 Toradex
 */

// Verdin DSI to LVDS Adapter orderable at Toradex.

/dts-v1/;
/plugin/;

/ {
	compatible = "toradex,verdin-imx8mp";
};

#include "verdin-imx8_mipi-dsi-to-sn65dsi84.dtsi"
#include "display-rvt50hqlnwc00b_sn65dsi84_overlay.dtsi"

&atmel_mxt_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&gpu_2d {
	status = "okay";
};

&gpu_3d {
	status = "okay";
};

/* LCDIF to MIPI-DSI */
&lcdif1 {
	status = "okay";
};

&mix_gpu_ml {
	status = "okay";
};

&ml_vipsi {
	status = "okay";
};

&vpu_g1 {
	status = "okay";
};

&vpu_g2 {
	status = "okay";
};

&vpu_vc8000e {
	status = "okay";
};

&vpu_v4l2 {
	status = "okay";
};

&reg_dsi_lvds {
	/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
	gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
};

  • tcbuild.yaml:
input:
  easy-installer:
    local: images/torizon-core-docker-verdin-imx8mp-Tezi_6.8.1+build.25.tar
customization:
  device-tree:
    include-dirs:
      - linux/include/
    custom: linux/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts
    overlays:
      add:
        - device-trees/overlays/verdin-imx8mp_dsi-to-lvds_panel-cap-touch-5inch-lvds_overlay.dts
output:
  easy-installer:
    local: build/torizon-core-docker-verdin-imx8mp-Tezi_6.8.1+build.25.tar.CUSTOM

Below are the issues we are facing with the overlays:

Setting Observed Behavior
data-mapping: vesa-24 Display does not work correctly (image: vesa24-selb-8bit-display.jpg)
data-mapping: jeida-24 Colors on display appear dimmed (image: jeida24-selb-8bit-display.jpg)


According to the display’s datasheet, the correct data-mapping is VESA. It is confusing that we need to set Jeida, which is not appropriate. On our custom board, the native LVDS display works fine with the nominal VESA-24 settings. What could be causing this issue?

Additionally, we are facing another problem with the color output. When the display is set to 8-bit input (SELB pin tied to High), the colors appear dimmed. However, when we switch it to 6-bit mode (SELB pin tied to Low), the colors look correct (image: jeida24-selb-6bit-display.jpg). How can we properly configure the 8-bit mode in the device tree while using the DSI-to-LVDS bridge?

Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!

Did you like my answer?

:+1: :-1:


Hello,

Thank you for reaching out with your display configuration concerns on the Verdin iMX8M Plus module. Here are some key points and suggestions to help address the issues you’re facing:

  1. Preferred Interface: For the Verdin iMX8M Plus, using the MIPI DSI interface with a DSI-to-LVDS adapter is recommended over direct LVDS connections. This is due to the module-specific nature of LVDS signals, which may not be universally compatible across different Verdin modules.

  2. Color Mapping Standards: The LVDS interface supports two color-mapping standards:

    • “24-bit, 18-bit compatible” (JEIDA format)
    • 24-bit mapping standard (VESA format)

    If you notice discrepancies, it might be due to how the DSI-to-LVDS bridge chip interprets these formats. Sometimes, the bridge chip may invert the expected format, which could explain why JEIDA works better even if your display specifies VESA.

  3. Color Depth Configuration: If you experience dimmed colors in 8-bit mode, this might indicate a mismatch in color data transmission through the DSI-to-LVDS conversion. Ensure that your color depth settings align with your display’s requirements.

Recommendations:

  • Double-check the configuration of your DSI interface, as it is the recommended approach for the Verdin iMX8M Plus.
  • Consider using a DSI-to-LVDS bridge on the carrier board for better compatibility.
  • Experiment with different combinations of color mapping settings, color depth configurations, and DSI-to-LVDS bridge chip settings to find the optimal setup for your display.

I hope these suggestions help you resolve the issues. If you have further questions or need more detailed guidance, feel free to ask.

Best regards,
Toradex AI Assistant.

Please, also check if these links can help you solve your problem:

Verdin iMX8M Plus | Toradex Developer Center.

Hello @szymon.politowski,

Welcome to the Toradex Community!
Sorry for the delay here and thanks a lot for the detailed description of the issue.

I think it is caused by a problem with the physical connection of the LVDS_1_A_TX3 signal.

The reason for this is that:

  • Given that you have a VESA-24 display, if that signal was missing, you would lose the most-significant bits of your picture, with the least significant bits being the same, which could explain the first picture you sent.
    • For each channel: b7 b6 b5 b4 b3 b2 b1 b00 0 b5 b4 b3 b2 b1 b0
  • If you instead configure the output to be JEIDA-24, the display still does not receive the most significant bits of your image, but, from the transmitter side, they are still transmitted and displayed in the 6 least significant bits. This explains the second, dimmed image that you sent.
    • For each channel: b7 b6 b5 b4 b3 b2 b1 b00 0 b7 b6 b5 b4 b3 b2
  • If you configure the display to expect 18-bits, then it will ignore TX3 and use a mapping that is compatible with JEIDA24.

VESA-24:

“VESA-18”:

JEIDA-24:

Best Regards,
Bruno

You are right - there is an issue with the physical connection of LVDS_1_A_TX3. We measured the LVDS_1_A_TX3_P and LVDS_1_A_TX3_N signals with an oscilloscope, and instead of a clear signal, we observed a significantly lower singnal compared to the other lanes. An optical inspection did not reveal any shorts or discontinuities near the FFC connector. However, when we tested with multimeters, it clearly indicated a short between these two signals.

After fixing this short, the display started to work with nominal parameters (vesa-24, 8bit).

Thank you for your quick response and for spotting this error.

Hello @szymon.politowski,

Thanks for the update.
It is good to know that you were able to get this resolved.

Best Regards,
Bruno