IMX8MM PCIe CLK

Technical Support
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Hi everyone!

I`m developing PCIe driver for QNX and strugglilng a problem with having access to PCIE controller regisers (i think that some of clock lanes not enabled).

Linux log prints me: [ 1.273916] imx6q-pcie 33800000.pcie: PCIe PLL locked after 0 us.
So, my QNX driver founded on https://github.com/nxp-imx/linux-imx/blob/imx_5.4.70_2.3.0/drivers/pci/controller/dwc/pci-imx6.c prints me → PCIe PLL lock timeout.

The simple write to IMX8MM_CLK_PCIE1_ROOT (CCGR37) register doesn`t make any difference.

Is there any special initialization sequence for CCM or for PCIe Controller?

Thanks!

2

All details about clock management are described in Chapter 5.1, “Clock Control Module (CCM),” in the i.MX 8M Mini Applications Processor Reference Manual. Since clock management isn’t a feature of the Toradex SOM but a property of the iMX8MM SOC, I recommend consulting the NXP community for further questions

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Thanks a lot.