iMX8M-Plus using some GPIO inputs with internal pullups

Hi,

We have a product using Verdin iMX8M-Plus 1.0D.
We want to have internal pull ups at ports GPIO_SODIMM_30 which is GPIO3_IO25 and GPIO_SODIMM_32 which is GPIO3_IO22.

Therefore I modified dts file as below:

/*
GPIO control bits: PE  HYS  PUE  ODE  FSEL  X  DSE1  DSE0  X
-----------------
Pull Select Field       : PE_0_PULL_DISABLE / PE_1_PULL_ENABLE
Input Select Field      : HYS_0_CMOS / HYS_1_SCHMITT
Pull Up / Down Config.  : PUE_0_WEAK_PULL_DOWN / PUE_1_WEAK_PULL_UP
Open Drain Field        : ODE_0_OPEN_DRAIN_DISABLE / ODE_1_OPEN_DRAIN_ENABLE
Slew Rate Field         : FSEL_0_SLOW_SLEW_RATE / FSEL_1_FAST_SLEW_RATE
Drive Strength Field    : DSE_X1 / DSE_X2 / DSE_X4 /DSE_X6
-----------------
Example: 0b010010110 -> 0x096 (PE_0_PULL_DISABLE | HYS_1_SCHMITT | PUE_0_WEAK_PULL_DOWN | ODE_0_OPEN_DRAIN_DISABLE | FSEL_1_FAST_SLEW_RATE | DSE_X6)
Example: 0b111110110 -> 0x1F6 (PE_1_PULL_ENABLE | HYS_1_SCHMITT | PUE_1_WEAK_PULL_UP | ODE_1_OPEN_DRAIN_ENABLE | FSEL_1_FAST_SLEW_RATE | DSE_X6)
*/

&iomuxc {
    pinctrl-0 = <&pinctrl_additionalgpio>;

    pinctrl_additionalgpio: additionalgpios {
        fsl,pins = <
            MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22          0x140               /* SODIMM 32    - PWR_2_VALID with PU */
            MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25          0x140               /* SODIMM 30    - PWR_1_VALID with PU */
        ...
        ...
        >;
    };
};

But I can not observe any pullup on the SODIMM pins 30 and 32 when they are inputs. When I assemble external pullup, below command returns 1 and 0 as expected. But once I remove external pullups, I always get zero.

root@verdin-imx8mp-06976886:~# gpioget 2 22
0

root@verdin-imx8mp-06976886:~# gpioget 2 25
0

root@verdin-imx8mp-06976886:~# cat /sys/kernel/debug/gpio
gpiochip0: GPIOs 0-31, parent: platform/30200000.gpio, 30200000.gpio:
 gpio-0   (                    )

gpiochip1: GPIOs 32-63, parent: platform/30210000.gpio, 30210000.gpio:
 gpio-32  (                    )
 gpio-42  (                    |id                  ) in  hi IRQ
 gpio-43  (                    |regulator-wifi-en   ) out hi
 gpio-44  (                    |cd                  ) in  hi IRQ ACTIVE LOW
 gpio-52  (                    |regulator-module-eth) out hi
 gpio-61  (                    |CTRL_SLEEP_MOCI#    ) out hi

gpiochip2: GPIOs 64-95, parent: platform/30220000.gpio, 30220000.gpio:
 gpio-64  (                    )
 gpio-83  (                    |led_status_1        ) out lo
 gpio-84  (                    |led_red             ) out lo
 gpio-90  (                    |scl                 ) out lo
 gpio-91  (                    |sda                 ) in  lo

gpiochip3: GPIOs 96-127, parent: platform/30230000.gpio, 30230000.gpio:
 gpio-96  (                    |Wake-Up             ) in  hi IRQ ACTIVE LOW
 gpio-98  (                    |led_status_2        ) out lo
 gpio-115 (                    |reset               ) out hi ACTIVE LOW
 gpio-118 (                    |regulator-usdhc2    ) out lo
 gpio-121 (                    |led_green           ) out lo

gpiochip4: GPIOs 128-159, parent: platform/30240000.gpio, 30240000.gpio:
 gpio-128 (                    )
 gpio-137 (                    |spi_imx             ) out hi
 gpio-142 (                    |scl                 ) out lo
 gpio-143 (                    |sda                 ) in  lo
 gpio-144 (                    |scl                 ) out lo
 gpio-145 (                    |sda                 ) in  lo
 gpio-148 (                    |scl                 ) out lo
 gpio-149 (                    |sda                 ) in  lo

Any suggestion?

Thank you.

Hi @Fide,

Can you please provide us with more information about your setup? Which carrier board and BSP version are you using?

In the meanwhile, we’ll try to reproduce this on our side.

Best regards,
Hiago.

Hi Hiago,

This is with our custom carrier board with the BSP v5.6.0

Thank you.

Have you removed that pins from this group?

Hi @alex.tx,

Thank you for the suggestion.

No actually I didn’t touch any toradex specific dtsi file. But of course we included that file in our custom dst file. None of the SAI modules are enabled, all have status = "disabled". Still shall we remove them? What is the proper way of removing those pins without touching imx8mp-verdin.dtsi file?

I added following lines into root of our custom dst file, it is compiled, I put it into the device, reboot but still no pull ups.

/delete-node/ &sai1;
/delete-node/ &sai3;

/delete-node/ &pinctrl_sai1;
/delete-node/ &pinctrl_sai3;

Hi @hfranco.tx,

Any update on your side?

Thank you.

Hi @Fide,

Could you please share the entire device tree that you created? So we can have a deeper look into it.
Have you tried with another carrier board? Did you see the same problem?

Best regards,
Hiago.

Hello @hfranco.tx

Here is the entire device tree:

/dts-v1/;

#include "imx8mp-verdin.dtsi"

/ {
    model = "Toradex Verdin iMX8M Plus WB on GPR Array";
    compatible = "toradex,verdin-imx8mp-wifi-gprarray",
             "toradex,verdin-imx8mp-wifi",
             "toradex,verdin-imx8mp",
             "fsl,imx8mp";

    /* Carrier Board Supply +V1.8 */
    reg_1p8v: regulator-1p8v {
        compatible = "regulator-fixed";
        regulator-max-microvolt = <1800000>;
        regulator-min-microvolt = <1800000>;
        regulator-name = "+V1.8_SW";
    };

    /* Carrier Board Supply +V3.3 */
    reg_3p3v: regulator-3p3v {
        compatible = "regulator-fixed";
        regulator-max-microvolt = <3300000>;
        regulator-min-microvolt = <3300000>;
        regulator-name = "+V3.3_SW";
    };

    reg_wifi_en: regulator-wifi-en {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_wifi_pwr_en>;
        regulator-name = "PDn_AW-CM276NF";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        startup-delay-us = <2000>;
    };

    gpioleds {
        compatible = "gpio-leds";
        pinctrl-names = "default";
        pinctrl-0 = <&leds_pins>;

        led@0 {
            label = "led_green";
            gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
            default-state = "off";
        };

        led@1 {
            label = "led_red";
            gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
            default-state = "off";
        };

        led@2 {
            label = "led_status_1";
            gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
            default-state = "off";
        };

        led@3 {
            label = "led_status_2";
            gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
            default-state = "off";
        };
    };

    pwmleds {
        compatible = "pwm-leds";

        led@0 {
            label = "power";
            pwms = <&pwm1 0 2000000 0>;
            max_brightness = <255>;
            /* For boot indication */
            linux,default-trigger = "pattern";
            led-pattern = <0 500 255 500>;
        };
    };
/*    
    altera_region {
        compatible = "fpga-region";
        fpga-mgr = <&altera_spi>;
        firmware-name = "test.rbf";
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
    };
*/
};

    /delete-node/ &sai1;
    /delete-node/ &sai3;
    
    /delete-node/ &pinctrl_sai1;
    /delete-node/ &pinctrl_sai3;  


/* Verdin SPI_1 */
&ecspi1 {
    status = "okay";

    spidev00: spidev@0 {
        compatible = "toradex,evalspi";
        reg = <0>;
        spi-max-frequency = <60000000>;
        status = "okay";
    };
/*
    altera_spi: altera-spi@0 {
        compatible = "altr,fpga-arria10-passive-serial";
        spi-max-frequency = <80000000>;
        reg = <0>;
        nconfig-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
        nstat-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>;
        confd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;          
    };
*/            
};

&eqos {
    status = "okay";
};

/* Verdin QSPI_1 */
&flexspi {
    status = "okay";
};

/* Verdin PCIE_1 */
&pcie {
    epdev_on-supply = <&reg_3p3v>;
    status = "okay";
};

&pcie_phy{
    status = "okay";
};

/* Verdin PWM_1 */
&pwm1 {
    status = "okay";
};

&reg_usdhc2_vmmc {
    vin-supply = <&reg_3p3v>;
};

/* Verdin UART_1 */
&uart1 {
    status = "disabled";
};

/* Verdin UART_2 */
&uart2 {
    status = "disabled";
};

/* Verdin UART_3, used as the Linux Console */
&uart3 {
    status = "okay";
};

/* Verdin UART_4 */
/* Often used by the M7 and then should not be enabled here. */
&uart4 {
    status = "disabled";
};

/* Verdin USB_1 */
&usb3_phy0 {
    status = "okay";
};

&usb3_0 {
    status = "okay";
};

/*    dr_mode = "peripheral";            */
/*    maximum-speed = "super-speed";     */
/*    /delete-property/ extcon;          */
/*    /delete-property/ hnp-disable;     */
/*	  /delete-property/ srp-disable;     */
/*	  /delete-property/ adp-disable;     */
/*    usb-role-switch;                   */
/*    status = "okay";                   */


&usb_dwc3_0 {
    status = "okay";
};

/* Verdin USB_2 */
&usb3_phy1 {
    status = "okay";
};

&usb3_1 {
    status = "okay";
};

&usb_dwc3_1 {
    status = "okay";
};

/* Verdin SD_1 */
&usdhc2 {
    status = "okay";
};

/* BEGIN On-module Wi-Fi */
/*************************/
&usdhc1 {
    bus-width = <4>;
    keep-power-in-suspend;
    max-frequency = <100000000>;
    non-removable;
    pinctrl-names = "default", "state_100mhz", "state_200mhz";
    pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>;
    pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi_ctrl>;
    pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi_ctrl>;
    vmmc-supply = <&reg_wifi_en>;
    wifi-host;
    status = "okay";
};

&gpio3 {
    gpio-line-names = "";
};

&gpio4 {
    gpio-line-names = "";
};
/*************************/
/* END On-module Wi-Fi */

/* Verdin I2C_2_DSI */
&i2c2 {
    clock-frequency = <400000>;
    pinctrl-names = "default", "gpio";
    pinctrl-0 = <&pinctrl_i2c2>;
    pinctrl-1 = <&pinctrl_i2c2_gpio>;
    scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    status = "okay";
};

/* Verdin I2C_1 */
&i2c4 {
    status = "okay";
};

/* Verdin I2C_3_HDMI */
&i2c5 {
    clock-frequency = <400000>;
    pinctrl-names = "default", "gpio";
    pinctrl-0 = <&pinctrl_i2c5>;
    pinctrl-1 = <&pinctrl_i2c5_gpio>;
    scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    status = "okay";
};

/*
GPIO control bits: PE  HYS  PUE  ODE  FSEL  X  DSE1  DSE0  X
-----------------
Pull Select Field       : PE_0_PULL_DISABLE / PE_1_PULL_ENABLE
Input Select Field      : HYS_0_CMOS / HYS_1_SCHMITT
Pull Up / Down Config.  : PUE_0_WEAK_PULL_DOWN / PUE_1_WEAK_PULL_UP
Open Drain Field        : ODE_0_OPEN_DRAIN_DISABLE / ODE_1_OPEN_DRAIN_ENABLE
Slew Rate Field         : FSEL_0_SLOW_SLEW_RATE / FSEL_1_FAST_SLEW_RATE
Drive Strength Field    : DSE_X1 / DSE_X2 / DSE_X4 /DSE_X6
-----------------
Example: 0b010010110 -> 0x096 (PE_0_PULL_DISABLE | HYS_1_SCHMITT | PUE_0_WEAK_PULL_DOWN | ODE_0_OPEN_DRAIN_DISABLE | FSEL_1_FAST_SLEW_RATE | DSE_X6)
Example: 0b111110110 -> 0x1F6 (PE_1_PULL_ENABLE | HYS_1_SCHMITT | PUE_1_WEAK_PULL_UP | ODE_1_OPEN_DRAIN_ENABLE | FSEL_1_FAST_SLEW_RATE | DSE_X6)
*/

&iomuxc {
    pinctrl-0 = <&pinctrl_additionalgpio>;
    
    pinctrl_i2c5: i2c5grp {
        fsl,pins = <
            MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL             0x400001c6  /* SODIMM 59 - SOM_TWI3_SCL */
            MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA             0x400001c6  /* SODIMM 57 - SOM_TWI3_SDA */
        >;
    };

    pinctrl_i2c5_gpio: i2c5grp_gpio {
        fsl,pins = <
            MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26           0x400001c6  /* SODIMM 59 - SOM_TWI3_SCL */
            MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27           0x400001c6  /* SODIMM 57 - SOM_TWI3_SDA */
        >;
    };

    leds_pins: led0grp {
        fsl,pins = <
            MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25               0x096 /* SODIMM 17 - LED_GREEN */
            MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20               0x096 /* SODIMM 19 - LED_RED */
            MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19              0x096 /* SODIMM 34 - LED_STATUS_1 */
            MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x096 /* SODIMM 36 - LED_STATUS_2 */
        >;
    };

    pinctrl_flexspi0: flexspi0grp {
        fsl,pins = <
            MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK       0x1c2   /* SODIMM 52 - SOM_QSPI_CLK */
            MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B    0x82    /* SODIMM 54 - SOM_QSPI_CS */
            //MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16     0x82    /* SODIMM 64 - NOT USED */
            MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS        0x82    /* SODIMM 66 - SOM_QSPI_DQS */
            MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00  0x82    /* SODIMM 56 - SOM_QSPI_DATA0 */
            MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01  0x82    /* SODIMM 58 - SOM_QSPI_DATA1 */
            MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02  0x82    /* SODIMM 60 - SOM_QSPI_DATA2 */
            MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03  0x82    /* SODIMM 62 - SOM_QSPI_DATA3 */
        >;
    };

    pinctrl_additionalgpio: additionalgpios {
        fsl,pins = <
            MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22          0x140               /* SODIMM 32    - PWR_2_VALID with PU */
            MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25          0x140               /* SODIMM 30    - PWR_1_VALID with PU */
            MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20          0x096               /* SODIMM 38    - FPGA_CDONE */
            MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00         0x096               /* SODIMM 206   - SOM_FPGA_IO0 */
            MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28          0x096               /* SODIMM 21    - SOM_GPS_RST */
            MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05         0x096               /* SODIMM 210   - SOM_FPGA_IO1 */
            MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06         0x096               /* SODIMM 212   - SOM_FPGA_IO2 */
            MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07         0x096               /* SODIMM 216   - SOM_FPGA_IO3 */
            MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01           0x096               /* SODIMM 222   - FE_POWER_EN */
            MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00           0x96                /* SODIMM 42    - FPGA_CONFIG */
            MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31          0x96                /* SODIMM 44    - FPGA_STATUS */
            MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01           0x96                /* SODIMM 46    - IMU_INT */
            MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2          0x106               /* SODIMM 91    - CLKOUT2 */
        >;
    };
};

Thank you.