Hi, we have some troubles defining the second ethernet port using device tree overlays.
We have noticed, using the Toradex Pinout designer that the MDIO and MDC pins are shared for the two ethernet ports.
Defining the ethphy2 in the fec1 as for the ethphy1 we were able to make the second eth port work but we are not able to set Phy parameters like as “micrel,led-mode” or “max-speed”.
It seems like as the second phy is ignoring those parameters.
We defined the fec2 in this way in our overlay dts:
/* Colibri FastEthernet */
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
phy-mode = "rmii";
phy-handle = <ðphy0>;
fsl,magic-packet;
fsl,wakeup_irq = <0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
micrel,led-mode = <1>;
reg = <2>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
micrel,led-mode = <1>;
reg = <1>;
};
};
};
/* Colibri FastEthernet 2 ETH2 */
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
fsl,magic-packet;
fsl,mii-exclusive;
status = "okay";
};
&iomuxc {
/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61
>;
};
// Pin per la seconda Ethernet
pinctrl_fec2: fec2grp {
fsl,pins = <
IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x60 // SODIMM 62
IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x60 // SODIMM 76
IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x60 // SODIMM 48
IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x60 // SODIMM 60
IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x60 // SODIMM 74
IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x60 // SODIMM 46
IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x60 // SODIMM 80
//IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 // SODIMM 184
//IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 // SODIMM 180
IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x60 // SODIMM 50
>;
};
};
The output of the “dmesg” command is the following:
[ 8.657179] 001: Micrel KSZ8041 5b040000.ethernet-1:01: attached PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=5b040000.ethernet-1:01, irq=POLL)
[ 8.708805] 000: Micrel KSZ8041 5b040000.ethernet-1:02: attached PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=5b040000.ethernet-1:02, irq=POLL)
[ 9.662718] 000: fec 5b050000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx
[ 9.662779] 000: IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[ 29.182692] 000: fec 5b040000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
[ 29.182749] 000: IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 31.709955] 001: 3.3V: disabling
What are we doing wrong?
Thanks in advance for the support.