[IMX8] iomuxc CONFIG parameter dts


I’m trying to create my own device tree source file based on the fsl-imx8qm-apalis-v1.1.dtsi file.

I’ve started to simply add some regular output pins using the iomuxc peripheral, like so:

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <

	apalis-imx8qm {
		pinctrl_debug_leds: debugledsgrp {
			fsl,pins = <
				/* Pins for the debug LEDs */
				SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02   0x00000021      /* SODIMM 13 */
				SC_P_MLB_SIG_LSIO_GPIO3_IO26       0x00000021      /* SODIMM 15 */

What I fail to understand though, is what the “0x00000021” comes from.
I understand that this describes the options for the IO pin but I’m unable to find any information about what this value represents and how to determine my own value.

I’ve read that this should be described in the iMX8 reference manual but I’m unable to find any references to this “CONFIG” parameter of the configuration.

Can someone point me in the right direction so I can determine my own CONFIG values?

By the way, can someone explain to me why “SC_P_xxxx” definitions are used instead of “MX8MQ_IOMUXC_xxxx” definitions, like I’ve seen in other examples?

Thanks in advance.

I’m not an expert, but I was wondering the same thing a few weeks ago. I couldn’t find a manual from NXP (might it still be under NDA?)

However, if you download the Pins Tool from NXP you can create a project for the SOC, select the pins in question (and their function), and then you have a panel at the bottom where you can select different options for the pins (and functions). Then, on the right side you have a panel with “Code Preview”, where you can find a DTS file. I just tried a few options until the numbers matched.

For SC_P_MLB_SIG_LSIO_GPIO3_IO26 I get the following:

  • 0x00000020 is pull-up
  • 0x00000001 is low drive strength

And I believe it’s the same for SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02

You need an account to download the software, but that’s free.


Hope that helps you along the way a little!



Hi Marcel,

This document is useful (from System Controller Firmware 101 - Pad configuration... - NXP Community)

Configuration under Linux

Linux configures pads through the device tree, the full documentation of the binding is under Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt. but here is an extract:

* Freescale i.MX8QXP IOMUX Controller

Required properties:
- compatible: "fsl,imx8qxp-iomuxc"
- fsl,pins: each entry consists of 2 integers. Its format is
 <pin_id pin_config>.

pin_config definition:
- i.MX8QXP have different pad types, please refer to below pad
 register definitions, the pinctrl driver will just write the
 pin_config into the hardware register.‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

The driver uses the following API:

sc_err_t sc_pad_set_gp (sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl) ‍‍‍

Instead of configuring each parameter individually as done with sc_pad_set_gp_28fdsoi it configures the pad as if writing to a register, the bitfield format is under the binding documentation but it is as follows:

struct _hw_pad_iomux_bitfields0
 uint32_t GP : 19; /*!< [18:0] GP controls. */
 uint32_t WAKEUP : 3; /*!< [21:19] Wakeup controls. */
 uint32_t WAKEUP_ENB : 1; /*!< [22] Wakeup write enable. */
 uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */
 uint32_t CONFIG : 2; /*!< [26:25] Config. */
 uint32_t IFMUX : 3; /*!< [29:27] Mux. */
 uint32_t GP_ENB : 1; /*!< [30] GP write enable. */
 uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */
 } B;

All the configurations mentioned above can be configured, but they are done in a single pass, e.g. Muxing, Configuration (Norma, Open Drive, etc…), Wakeup control, and GP controls are for Pull Select Drive Strenght etc… Check the Reference Manual Chapter for IOMUXD for the register definition for each pad.