iMX7 SPI pin mapping with 2 chip selects using Toradex pin designer

My design utilizes SPI with 2 chip selects. I have 1 chip select working with the FreeRtos polling example. Setting up the 2nd chip select is a problem.

Refering to the Pin Designer screen shot, I tried to use pin SOM pin 101 as the 2nd chip select. In the main.c file I changed

.channelSelect = BOARD_ECSPI_CHANNEL


.channelSelect = ecspiSelectChannel1

Where as the ecspiSelectChannel0 activated CS0, ecspiSelectChannel1 left SS0 inactive, but failed to activate SS1 on pin 101.

Looking at the Pin Designer with CS1 configured on pin 101 I am concerned that SS1 is NOT a member of the function entries column I’ve circled in red.
ecspi3.SCLK, ecspi3.SS0, ecspi3.MISO, etc
Does this mean I manually have to activate the 2nd chip select as a GPIO bit?

What reinforces this thinking in the lower part of the screen shot I’ve configured CS1 as pin 53, which now shows ecspi3.SS1 as a legitimate member of the SPI interface. However, it conflicts with SD_1_DATA3.

Also a question on the Pin Designer columns:

  • imx7_512MB_Function : shows ecspi3
  • imx7_512MB Pin SoC: shows ECSPI1_xx

The FreeRTOS board.h has a comment that Colibri SPI is on ecspi3 which gives credance to the imx7_512MB_Function column as being correct.

If I want to look at other alternative SPI ports, they conflict in some major way. If I had to guess, I would have to use CS1 on pin 53 to get a working SPI port with 2 chip selects. Is this correct?

What is best way to proceed?

PinoutDesigner Screenshot

Dear @bobpbbd104

Let me start with some background information and explanations:


  • SoM (System on Module) is a term we use to describe the entire module, the Colibri iMX7D in this case.
  • SoC (System on Chip) is a term we use to describe the main chip, the NXP i.MX7 Dual application processor in this case.

Pin Naming

As you probably know the IOs of the SoC can be multiplexed to a number of different SoC functions. It can be confusing to differentiate between the different namings:

  1. The SoC-internal function which can be selected by choosing the correct pin muxing.
    e.g. ecspi3.SS1
  2. The name which was chosen by NXP to name the i.MX7 BGA ball
    e.g. I2C2_SDA
  3. The name which was chosen by Toradex to have a common name across all modules
    e.g. SPI_1_MASTER_CS1

I didn’t see the actual pin you were referring for the question ecspi3 vs ECSPI1_xx, but it means that
a articular SoC Pin can be multiplexed to either ecspi1 o ecspi3; NXP decided to use the ECSPI1 name for the BGA ball, but you selected the ecspi3 feature.

Pin 101

Pin 101 can be used as CS1 on some Colibri modules, but not on the Colibri iMX7D. This is the reason why you see this cell empty in the Pinout Designer. If you select only the Colibri iMX7D in the Modules menu, this pin will not be shown in the SPI section at all.


I see 3 resonable options to use the standard SPI port (ecspi3) with two chip selects:

  1. The hardware chip select ecspi3.SS1 is only available Use on SODIMM pin 53. From an SPI point of view this would be the best solution, but you lose the SD card interface.
  2. Emulate the chip-select by toggling a GPIO before and after the SPI transfer. This gives you the flexibility of choosing any pin, but of course needs some software overhead and will slightly impact the performance.
    This is probably the way to go if you want to be compatible to future Colibri modules.
  3. On the Colibri iMX7D, ecspi.SS0 is available on two SODIMM pins (34 and 86). Instead of switching the chip select between SS0 and SS1, you could switch the alternate function of these two pins: configure one as ecspi.SS0, and the other as GPIO, output, high. Doing an SPI transfer will only toggle the pin which is configured as chip select.

Regards, Andy

Thanks Andy for your quick response. A followup please:

I tried Toradex SPI 2,3 and cross-checked with the iMX7D_512MB_Function column.

Case of Toradex SPI 2 - As shown in the attached screen-shot there seems to be a successful mapping to ecspi1.SS0, MISO, MOSI. But why is there no Toradex pin selection that results in a legitimate entry for the CLK in this column? It seems if the chip fundamentally supports ecspi1 then shouldn’t the CLK also be there?

Case of Toradex SPI 3 - There are no successful mappings shown in the iMX7D_512MB_Function column. The iMX7 supports 4 ecspi ports, so shouldn’t there be a match?

Case of Toradex SPI 4 - No CLK is shown, assume it’s a bug?

For some reason my attachments are not showing up in my preview.
[This post was edited to show the screenshots]


Dear @bobpbbd104

There is a minor bug in the Pinout Designer database for iMX7: the SPI clock signal is named SPI_2_MASTER_SCLK instead of SPI_2_MASTER_CLK, so you see both entries in the tree view, which actually should be combined into one row.

I added a ticket in our bug tracking system to have this fixed. Meanwhile just select both signals in the tree view, and ignore that the tool shows the two signals being in conflict.

Regards, Andy