iMX7 Linux and FreeRTOS sharing ram

Hi everyone,

Our objective is to analyze the timing performance of the M4 with FreeRTOS, having Linux in the A7. Therefore, we think that a interest test is to stress the DDR from Linux and to see if the M4 tasks suffers any latency. However, we have seen some weird things.

  • The MCIMX7D_M4_ddr.ld sets the code
    in the DDR but the data in the TCM.
    Is it possible to set it in the DDR?
  • Apart from that, the
    imx7d-colibri-aster.dts” sets all the
    memory for Linux. Is it necessary to
    create a new DTB limiting the memory address?
  • How does the AXI busmanage the priorities? The M4 has the higher priority? If the A7 and M4 try tio write in the DDR at the same time, which one has priority?

Thank you!

  • Any combination is possible. The linker file provided by the Toradex FreeRTOS BSP MCIMX7D_M4_ddr.ld uses DDR for all sections, hence for data/bss and code (text).
  • The device tree in the Linux kernel tree come with a default memory section which assigns all memory to Linux. However, U-Boot does dynamically update the memory node. The Colibri iMX7 board code furthermore reserves some memory for the M4 core in case it is running upon boot, see: board/toradex/colibri_imx7/colibri_imx7.c (ft_board_setup).
  • I don’t know how AXI exactly manages the priority. A quick glance in the i.MX 7Dual Reference Manual also does not reveal the answer. It seems that the Cortex-M4 is connected through AHB… I would expect some round-robin or similar mechanism.

That said, my own measurements have shown that running from DDR already is a major performance penalty, especially since most DDR code cannot used cached… If somehow possible I would try to run from TCM/OCRAM.

  • I use the Colibri board with the ARM DS-5 and I realized that the linker’s addresses are different to the between arm and gcc (.scf & .ld). Why?
  • Thank you!
  • I think it is RR, but I am not sure.

Another question, when does Linux use the OCRAM? Does it use the OCRAM by default for any specific task?

The linker file from DS-5 comes from NXP, I don’t know why they only run part of the firmware from DDR…

The NXP BSP based Linux kernel stores some structures during low-power in OCRAM, see arch/arm/mach-imx/pm-imx7.c. And I think the SDMA firmware also is in OCRAM, but I am not 100% sure on that. But the linker script we provide now uses EPDC OCRAM, which should be safe to use.

Do you know which are the start address and end address of the RAM for the M4? I can not find it in the code board/toradex/colibri_imx7/colibri_imx7.c.

We use the last 1MB of the DDR RAM location, 0x8ff00000-0x8fffffff (also available for the M4 code alias at 0x1ff00000-0x1fffffff. Be aware that running the firmware from DDR comes with a major speed penalty (see above).

That is 1MB space. However, if I boot Linux with the M4 running /proc/meminfo shows 1023728 kB and without M4 1025772 kB. The difference is 2MB. What is happening with the other 1MB?

This is due to historical reasons. We had to increase to 2MB due to Linux memory management limitations. Since there was no pressure to increase size of FreeRTOS firmware we did not change the linker file (again), so we left it as is. If required, it should be safe to change the linker file to make use of the additional space (just set 0xXff00000 to 0xXfe00000).

See also

I have seen that there was a MMDC Profiling Tool for iMX6. Is there anything for the imx7?

I want to know the bus utilization percentage. Is that possible in thisboard? I can not found any counter for that in the Reference Manual.

The i.MX 7 uses a different memory controller than the i.MX 6… I am also not aware of such capabilities. I guess this would be a question for the NXP Community…