iMX7 External Memory (EIM) consecutive async write - no ADV signal

Figure 9-61 of the i.MX7 reference manual shows a timing diagram for “Consecutive Asynchronous Write Memory Accesses Timing Diagram” which would presumbably represent writing a 32 bit value to an external device using the available 16 bit wide data bus. The only signal that separately identifies the two halves of the 32 bit word is the “ADV” signal. But despite considerable searching, I can’t find where this signal is available as an external pin on the i.MX7 ???

Figure 9-62 show the same scenario, with CSREC set to 2. In this diagram, there are lots of signals that differential the two half-words. Unfortunately, my external device (A/D converter) requires that the CS signal be asserted continuously for both of the half-words. Any suggestions on how to accomplish this ?

Thanks, Scott.

Unfortunately the timing diagrams signal names do not match one to one to the EIM signal names. But Table 9-25 has a nice overview of the signals by their EIM name. The signal you are looking for seems to be EIM_LBA_B (described as ADdress Valid, I guess that is where the short form ADV comes from). This signal is available on the SODIMM 150.

As for the CS (chip select), I guess you should use one of the EIM chip select signals (EIM_CS0-4). It seems that not all timing diagram include that signal, but when it is included it is denoted as CSo. I guess to have it continuously asserted you would have to set RCSA/RCSN/WCSA/WCSN to 0.