Figure 9-61 of the i.MX7 reference manual shows a timing diagram for “Consecutive Asynchronous Write Memory Accesses Timing Diagram” which would presumbably represent writing a 32 bit value to an external device using the available 16 bit wide data bus. The only signal that separately identifies the two halves of the 32 bit word is the “ADV” signal. But despite considerable searching, I can’t find where this signal is available as an external pin on the i.MX7 ???
Figure 9-62 show the same scenario, with CSREC set to 2. In this diagram, there are lots of signals that differential the two half-words. Unfortunately, my external device (A/D converter) requires that the CS signal be asserted continuously for both of the half-words. Any suggestions on how to accomplish this ?