Imx6dl, linux 5.x dunfell build, ipu1_di1 does not generate a pixelclk

Trying to get 2x parallel RGB outputs from the second display interface channel on IPU1 on the imx6dl. The first lcd channel works as expected (no issues). Have had no success displaying an image on lcd2 channel. please advise.

I have performed the following steps but for some reason the sodimm_45 pixelclk cannot be observed on a scope.

  1. Patched the kernel driver mxc_lcdif.c to include support for a second LCD

static struct mxc_dispdrv_driver lcdif_drv = { {
.name = DISPDRV_LCD,
.init = lcdif_init,
.deinit = lcdif_deinit,
}, {
.name = DISPDRV_LCD2,
.init = lcdif_init,
.deinit = lcdif_deinit,
} };

Revised imx6qdl-colibri.dtsi as shown with a limited set of pins for now for testing. On a scope, i observe sync pulses at 60hz refresh rate as expected.

lcd2: lcd@1 {
	compatible = "fsl,lcd";
	ipu_id = <0>;
	disp_id = <1>;
	default_ifmt = "RGB24";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_lcdif_ch2>;
	status = "disabled";
};

pinctrl_ipu1_lcdif_ch2: ipu1lcdifgrp2 {
	fsl,pins = <
		MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0xa1 //pixel clock
		MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02		0xa1 //HSYNC
		MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03		0xa1 //VSYNC
		MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15		0xa1 //ENABLE
		MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0xa1 //BLUE00

	>;
}; 

My custom .dts overlay activates the framebuffers as follows:-

&mxcfb1 {
compatible = “fsl,mxc_sdc_fb”;
disp_dev = “lcd”;
interface_pix_fmt = “RGB24”;
mode_str =“Aspire”;
default_bpp = <32>;
int_clk = <0>;
late_init = <0>;
status = “okay”;
};

&mxcfb2 {
compatible = “fsl,mxc_sdc_fb”;
disp_dev = “lcd2”;
interface_pix_fmt = “RGB24”;
mode_str =“Aspire”;
default_bpp = <32>;
int_clk = <0>;
late_init = <0>;
status = “okay”;
};

This issue has been resolved and was related to a hardware problem on the carrier board.