i.MX95 MIPI CSI-2 Camera Pipeline

Technical Support
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We are trying to understand the limitations of the NXP i.MX95 Camera Pipeline (MIPI CSI-2, ISI, ISP)

My concrete question is: What is the maximum resolution (with/height in pixel) the hardware pipeline can process.

Michael

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Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

I’d be glad to help with your i.MX95 MIPI CSI-2 camera pipeline question! However, to provide you with the most accurate information about hardware limitations and pipeline capabilities, I need to understand your specific setup better.

Could you please clarify:

  1. Which hardware platform are you using? For example:

    • Verdin iMX95
    • Aquila AM69
    • Another Toradex SoM with i.MX95

  2. Which OS and version are you running? Common platforms include:

    • Torizon OS (version?)
    • Yocto BSP (version like 7.2.0?)

  3. What carrier board are you using? Such as:

    • Verdin Development Board
    • Ivy Carrier Board
    • Custom carrier board

You can get detailed system information by running the tdx-info command on your device. This will help me provide specific guidance about the camera pipeline capabilities and maximum resolution limits for your exact configuration.

For more details about the tdx-info command, see: Getting Device Information with Tdx-Info | Toradex Developer Center

The camera pipeline specifications can vary significantly between different hardware configurations, so knowing your exact setup will ensure I give you accurate information about resolution limits and processing capabilities.

Best regards, Toradex AI Assistant.

Did you like my answer? :+1: :-1:

If I answered your question, please tick the “Solution” checkbox.

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3

Hardware Platform: Aquila iMX95
OS: Yocto BSP 7.2

4

I need to clarify something important about your setup. Based on the available documentation, there’s a key detail about the Aquila iMX95 that affects your BSP 7.2 usage.

According to the silicon revision update guide, the Aquila iMX95 V1.0A with B0 silicon is supported starting from BSP 7.5.0, not BSP 7.2(1). The compatibility matrix shows:

Aquila iMX95 Support:

  • V1.0A - B0: Supported starting from BSP 7.5.0(1)

This means BSP 7.2 may not provide full support for the Aquila iMX95’s camera pipeline capabilities. For accurate MIPI CSI-2 pipeline specifications and maximum resolution limits, you would need to upgrade to BSP 7.5.0 or later.

The documentation I have access to covers camera pipeline details for other i.MX platforms (like i.MX8M Plus, i.MX93, etc.), but doesn’t include specific technical specifications for the i.MX95 camera subsystem’s maximum resolution capabilities.

Recommendation:

  1. Upgrade to BSP 7.5.0 or later to ensure full Aquila iMX95 support(1)
  2. Check the i.MX95 reference manual from NXP for detailed ISI/ISP pipeline specifications
  3. You may find relevant technical discussions by searching the Toradex Community for “i.MX95 camera” or “Aquila camera pipeline”

Would you be able to test with a supported BSP version? This would ensure you get the full camera pipeline capabilities and accurate resolution limits for your Aquila iMX95 setup.

Best regards, Toradex AI Assistant.

Did you like my answer? :+1: :-1:

If I answered your question, please tick the “Solution” checkbox.

For follow-up questions to me, please use @ToradexAI in your post.

5

Hello @michael.koster,

On the i.MX95, there are different paths the captured video can take.
The exact limitations will depend on the number of cameras involved and the path taken by the video.

However, if you want to make use of the ISI or the ISP, a practical limitation is a maximum horizontal resolution of 4096.
Keeping the vertical resolution below 4096 is required for the ISP.

If you are just capturing video directly, with no processing, the ISI can pass the video directly to memory, only limited by the MIPI-CSI receiver which is capable of much larger resolutions.

What is your intended setup?
Does it involve multiple cameras?

For more information, I recommend that you refer to the i.MX95 Reference Manual:

  • Chapter 141 - Camera Domain Overview
  • Chapter 152 - Image Sensing Interface (ISI)
  • Chapter 153 - Image Signal Processing Pipeline (ISP - NEO) Overview

Best Regards,
Bruno

1 Like
6

We are looking into connecting a single AR2020 sensor capturing image frames with up to 25FPS
We will be needing to extract a subset (crop/rescale) of the acquired image. We want to offload this compute intense task to hardware. This is where ISP may come into play.

We intend to use binning and croping features of the sensor to get some of the work done.

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Hello @michael.koster,

Such setup would only be viable if you only receive up to 4096 horizontal resolution from the AR2020.
As you mentioned that you plan to use binning and cropping features of the sensor, the iMX95 could still be capable to handle your use case.

The ISP has no crop or rescale capabilities.
The ISI on the other hand has such capabilities.
If using a grayscale image and without the need for much correction, using the ISI directly would be an option.
Otherwise, using both ISP and ISI would be the way to go.

I see the following as a viable option on the iMX95:
AR2020 (outputting 4096x3840 or less) → MIPI-CSI → ISP → Memory → ISI → Memory (final frame)

Best Regards,
Bruno