dear all,
i’m working with the following configuration:
Apalis iMX8QM 4GB WB IT V1.1D
Ixora Carrier Board V 1.2A
Linux BSP 6.3.0
I want to use RGMII for information using the LCD on the ixora carrier board.
The RGMII we use must use 1.8v.
Can you help me create the device tree?
Additionally, can you tell me where the datasheet for setting up device tree Pin configuration register is located?
Can someone help me with this, pls?
Best regards,
dear all,
i’m working with the following configuration:
Apalis iMX8QM 4GB WB IT V1.1D
Ixora Carrier Board V 1.2A
Linux BSP 6.3.0
I would like to use RGMII information using the LCD of the ixora carrier board.
The RGMII we use must use 1.8v.
We configured the device tree as shown below.
/*
* Power management bus used to control LDO1OUT of the
*second PMIC PF8100. This is used for controlling voltage levels of
* typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
*
*IMX_SC_R_BOARD_R1 for 3.3V
* IMX_SC_R_BOARD_R2 for 1.8V
*IMX_SC_R_BOARD_R3 for 2.5V
* Note that for 2.5V operation the pad muxing needs to be changed,
* compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
*
*those power domains are mutually exclusive.
*/
reg_ext_rgmii: regulator-ext-rgmii {
compatible = "regulator-fixed";
regulator-name = "VDD_EXT_RGMII (LDO1)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* change to 1.8V power domain for external RGMII interface */
power-domains = <&pd IMX_SC_R_BOARD_R2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
......
/* External RGMII interface PHY */
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
fsl,magic-packet;
fsl,mii-exclusive;
phy-supply = <®_ext_rgmii>;
phy-handle = <ðphy1>;
phy-mode = "rgmii-id";
/* specify the corresponding reset GPIO pin according to your HW design */
/* if no phy reset is connected, appoint it to a un-used GPIO pin instead */
phy-reset-duration = <10>;
phy-reset-gpios = <&lsio_gpio2 23 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* please specify corresponding phy address according to HW design */
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
.....
pinctrl_fec2: fec2grp {
fsl,pins = <
IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020
IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020
IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M 0x06000020
IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020
IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020
IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020
IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020
IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020
IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020
IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020
IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020
IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020
IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020
IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020
IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020
/* On-module ETH_RESET# */
IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 0x06000020
/* On-module ETH_INT# */
IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 0x04000060
>;
};
I checked the RGMII_TXC voltage level by setting the device tree above, but it outputs at 2.5v. Can you help me set up RGMII 1.8V output?
Best regards,
sjjin