i.MX8MM QSPI Interface

Technical Support
, , ,
1

Does anybody have an example .dtsi file that configures the QSPI ports for 1x mode?

2

The QSPI interface is designed to acts as an interface to one or two external serial flash devices. And bus width is defined by connected flash device. So if we are going to use say Micron n25q256a we should set the QSPI flash compatible property as it described here. And Micron n25q256a supported modes are listed here.

3

Hi,

Actually normal QSPI memories support 1-, 2- and 4-pin buswidth modes. QSPI controllers, at least those from FSL as well support all modes. spi-nor.c driver doesn’t specify how many data lines each chip supports in struct flash_info. Instead it seems reading modes supported from chip and then tries to find best mode QSPI controller supports.

Usually CPUs with QSPI have plenty of pins and there’s no need to save 2 pins on slower QSPI modes. spi-fsl-qspi.c driver doesn’t support specifying bus width limit in DT (1-, 2- or 4 pins). It just answers all modes are supported:

static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
{
switch (width) {
case 1:
case 2:
case 4:
return 0;
}

return -ENOTSUPP;

}

If you absolutely need it, try suppressing cases 4 and 2, hope it will work.

Edward

4

Thank you both for the response, I am looking into them now.
I am using Yacto and am looking for something like this:
I have created these items in linux-toradex/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
&flexspi {
compatible = “nxp,imx8dxl-fspi”;
pinctrl-names = “default”;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = “okay”;

qspi0: qspi@0 {
	pinctrl-0 = <&pinctrl_flexspi0>;
	reg = <0>;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <100000>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <1>;
};

qspi1: qspi@1 {
	pinctrl-0 = <&pinctrl_flexspi1>;
	reg = <1>;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <100000>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <1>;
};

};

pinctrl_flexspi0: flexspi0grp { fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 /
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 / SODIMM 54 /
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 / SODIMM 56 /
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 / SODIMM 58 */
>;
};

pinctrl_flexspi1: flexspi1grp { fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2 /* SODIMM 76 /
MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 / SODIMM 162 /
MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 / SODIMM 164 /
MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 / SODIMM 21 */
>;
};

Does seem about right?

5

Hi @DanStallman,

Indeed yes, spi-tx-bus-width and spi-rx-bus-width apply here. What surprised me is that when these settings are not specified, default values for both are <1>, not <4>. Why??? At least it is so using spi-fsl-qspi driver. There are other odd things notified with default clocks, but it is not this thread question.

Regarding DT, interrupts, compatible and pinctrl-names are already specified in imx8mm.dtsi, which your *.dts file should include directly or indirectly via different *.dtsi includes. These settings differ with yours, please check them, as well check are you using imx8mm or indeed imx8dxl.

pinctrl-0 settings should be a property of controller, not property of chip used. Perhaps it will work as you specify, but usually they are specified in controller properties.

May you confirm your connection? One chip on QSPI_A, another on on QSPI_B, both are using QSPI_x_SS0_B? If so, then chip reg settings should be <1> and <3>, as well qspi@ should be 1 and 3 accordingly. 0 is for A_SS0_A, 1 for A_SSO_B, 2 for B_SSO_A, 3 for B_SSO_B

qspi0: qspi@1 {
	reg = <1>;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <100000>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <1>;
};

qspi1: qspi@3 {
	reg = <3>;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <100000>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <1>;
};

Since both DATA0 and DATA1 pins have to be used for single data bit mode, you may use 2 bit mode as well, unless you are doing something like single direction galvanic isolation.

Edward

6

Edward,
Thank you for the excellent info!
" MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 / SODIMM 54 /" & " MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 / SODIMM 21 *" are typo’s, thank you for catching that. One chip on QSPI_A, another on on QSPI_B.
Should be: QSPI0 - reg = <0>;
QSPI1 - reg = <2>;
imx8mm is the chip I am using.
Thanks again,
Dan