I am trying to upgrade the PXA270 Colibri to T20 and so far it seems to have been upgraded. I have changed the hardware connections, according to new pins, and VHDL code respectively and still the FPGA doesn’t communicate with T20.
How should I make the interface work between the Actel FPGA and T20 ?
The Data pins have shifted as well as the way you have to initialize the memory bus (SNOR) in a different way.
Check first the datasheet of the T20, where you find the differences explained on page 28. Either you do a hardware redesign or shift your data.
Second we provide some gettings started sample code for memory bus communication. Please be aware that this is only a sample and not production ready code yet. To understand all the details you also should get the Tegra T20 TRM.
I have changed the data pins but I am not sure about initialising the memory bus (SNOR). Can you please send me some information about it ?
I changed the pins on hardware and in VHDL code.
The pins on SODIMM are as follows and they are connected to the right FPGA pin.
PIN59 (“nSELECT”) is now PIN105 (“c_nCS1”)
PIN97 (“nPOE”) is now PIN91 (“c_nOE”)
PIN99 (“nPWE”) is now PIN89 (“c_nWE”)
I have also added T20 libraries to C++ project.
I am trying use the sample codes to understand memory bus communication but I appreciate more explanations or suggestions.
Please check the sample code for more details:
It shows you
- How to set the GPIOs,
- How to access the GMI Config registers
- How to set the right clock using the clock lib (get it from the Tegra WinCE Libraries site).
If you have any specific question please let us know.