Hello Toradex support,
Seems that I refined my search… Please, do forget what I wrote in my initial post!
I realize that I am a bit lost in this all i.MX8QM clocking tree Minotaur’s maze… I apologize for that!
Actually, what I need to do is the following:
From:
adb_shell: / # cd /sys/kernel/debug/clk
adb_shell: /sys/kernel/debug/clk # cat clk_summary
…[snap]…
mipi_pll_div2_clk 2 2 0 432000000 0 0 50000
mipi0_dsi_rx_esc_clk 0 0 0 72000000 0 0 50000
mipi0_dsi_tx_esc_clk 1 1 0 18000000 0 0 50000
mipi0_dsi_phy_clk 1 1 0 27000000 0 0 50000
mipi1_dsi_phy_clk 0 0 0 27000000 0 0 50000
I need to increase mipi_pll_div2_clk to at least from (27 MHz x 16) to (27 MHz x 24 or 32) to get the higher resolution for the MIPI0_DSI link. Since the resolution I need, covered by mipi_pll_div2_clk 2 2 0 432000000 0 0 50000 is not supported (2880 x 720).
How I can increase this clock to cover the following from the dts tree?
panel-timing {
clock-frequency = <137000000>;
hactive = <2820>;
vactive = <720>;
...[snap]...
};
As my best understanding is, there are 4 bits out of 24 (pixel size) transferred per 137 MHz which gives 137 MHz x 4 = 548 MHz (thus I need to increase mipi_pll_div2_clk from 432 MHz to 548 MHz)?
Thank you,
Zoran
_______ Initial Post _______
Hello Toradex support,
I am looking to redefine some i.MX8QM clock usages, namely the next SCU RPC call poses the vital interest to me:
in kernel/drivers/clk/imx/clk-imx8qxp.c the imx_clk_scu2() call shown below:
imx_clk_scu2(“mipi0_dsi_phy_clk”, mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
Where the params are:
[0] “mipi0_dsi_phy_clk” ==> resource, my best guess is:
uboot/include/dt-bindings/clock/imx8qm-clock.h
#define IMX8QM_MIPI0_DSI_PHY_CLK 797
[1] mipi_sels, defined in kernel/drivers/clk/imx/clk-imx8qxp.c
static const char *mipi_sels[] = {
"clk_dummy",
"clk_dummy",
"mipi_pll_div2_clk",
"clk_dummy",
"clk_dummy",
};
Where the unknown parameter to me is: “mipi_pll_div2_clk” (this is why I need these SCU FW definitions, since I need/should put there another divider)!
[2] ARRAY_SIZE(mipi_sels) = 5
[3] IMX_SC_R_MIPI_0, defined as resource in kernel/include/dt-bindings/firmware/imx/rsrc.h
#define IMX_SC_R_MIPI_0 393
[4] IMX_SC_PM_CLK_PHY, defined as clock in kernel/include/dt-bindings/firmware/imx/rsrc.h
#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
Any ideas where I can find these SCU FW definitions?
(I am using the following manual, not able to find them there: i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual, Rev. 0, 05/2020. Maybe these values are defined in some other manual… In which?)
Is there any other method how to change the mipi0_dsi_phy_clk freq?
Thank you,
Zoran
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