How to increase mipi_pll_div2_clk for the APALIS SOMs based on i.MX8QM and i.MX8QX?

Hello Toradex support,

Seems that I refined my search… Please, do forget what I wrote in my initial post!

I realize that I am a bit lost in this all i.MX8QM clocking tree Minotaur’s maze… I apologize for that!

Actually, what I need to do is the following:

From:

adb_shell: / # cd /sys/kernel/debug/clk
adb_shell: /sys/kernel/debug/clk # cat clk_summary

…[snap]…

mipi_pll_div2_clk 2 2 0 432000000 0 0 50000
mipi0_dsi_rx_esc_clk 0 0 0 72000000 0 0 50000
mipi0_dsi_tx_esc_clk 1 1 0 18000000 0 0 50000
mipi0_dsi_phy_clk 1 1 0 27000000 0 0 50000
mipi1_dsi_phy_clk 0 0 0 27000000 0 0 50000

I need to increase mipi_pll_div2_clk to at least from (27 MHz x 16) to (27 MHz x 24 or 32) to get the higher resolution for the MIPI0_DSI link. Since the resolution I need, covered by mipi_pll_div2_clk 2 2 0 432000000 0 0 50000 is not supported (2880 x 720).

How I can increase this clock to cover the following from the dts tree?

panel-timing {
        clock-frequency = <137000000>;
        hactive = <2820>;
        vactive = <720>;
        ...[snap]...
};

As my best understanding is, there are 4 bits out of 24 (pixel size) transferred per 137 MHz which gives 137 MHz x 4 = 548 MHz (thus I need to increase mipi_pll_div2_clk from 432 MHz to 548 MHz)?

Thank you,

Zoran

_______ Initial Post _______

Hello Toradex support,

I am looking to redefine some i.MX8QM clock usages, namely the next SCU RPC call poses the vital interest to me:

in kernel/drivers/clk/imx/clk-imx8qxp.c the imx_clk_scu2() call shown below:

imx_clk_scu2(“mipi0_dsi_phy_clk”, mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);

Where the params are:

[0] “mipi0_dsi_phy_clk” ==> resource, my best guess is:

uboot/include/dt-bindings/clock/imx8qm-clock.h
#define IMX8QM_MIPI0_DSI_PHY_CLK 797

[1] mipi_sels, defined in kernel/drivers/clk/imx/clk-imx8qxp.c

static const char *mipi_sels[] = {
"clk_dummy",
"clk_dummy",
"mipi_pll_div2_clk",
"clk_dummy",
"clk_dummy",
};

Where the unknown parameter to me is: “mipi_pll_div2_clk” (this is why I need these SCU FW definitions, since I need/should put there another divider)!

[2] ARRAY_SIZE(mipi_sels) = 5

[3] IMX_SC_R_MIPI_0, defined as resource in kernel/include/dt-bindings/firmware/imx/rsrc.h
#define IMX_SC_R_MIPI_0 393

[4] IMX_SC_PM_CLK_PHY, defined as clock in kernel/include/dt-bindings/firmware/imx/rsrc.h
#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */


Any ideas where I can find these SCU FW definitions?

(I am using the following manual, not able to find them there: i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual, Rev. 0, 05/2020. Maybe these values are defined in some other manual… In which?)

Is there any other method how to change the mipi0_dsi_phy_clk freq?

Thank you,
Zoran


Hi @_nobody,

In order to help you with this issue, could you please share more information about your setup with us?

  • Which BSP are you using? OS and version.
  • Are you using a custom carrier board? If so, can you share more information about your hardware?
  • Are you using some type of hardware controller for MIPI DSI?

Best regards,
Hiago.

Hello Hiago,

Thank you for your reply. The kernel I am using (for the automotive project) is one from the NXP. Actually this is the kernel suited to support Android 9+ versions. It is, after all, an Android project.

The kernel itself is the following:
uname -a
Linux localhost 5.4.47-g98322d6a6de6-dirty #60 SMP PREEMPT Wed Jun 15 05:41:22 Europe 2022 aarch64

So, it is a i.MX8QM silicon, defined by i.MX8QM defconfig file.

My best guess is that initial kernel, as also the number of back-ported elements come from the following repository: linux-imx - i.MX Linux kernel .

I am also attaching from /sys/kernel/debug/clk/clk_summary > clk_summary.txt for your review.

Here is also the failing part of the dmesg which shows that the generated clock of 822 MHz does not generate correct clocks:

[    4.009146] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_probe] Setup clk bypass (rate: 24000000)
[    4.009190] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_probe] Setup clk pixel (rate: 24000000)
[    4.009470] panel-raydium-rm67191 56228000.dsi_host.0: 56228000.dsi_host.0 supply v3p3 not found, using dumm>
[    4.020329] panel-raydium-rm67191 56228000.dsi_host.0: 56228000.dsi_host.0 supply v1p8 not found, using dumm>
[    4.031180] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_host_attach] lanes=4, format=0x0 flags=0x11
[    4.040030] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    4.046652] [drm] No driver support for vblank timestamp query.
[    4.052665] imx-drm display-subsystem: bound imx-drm-dpu-bliteng.2 (ops dpu_bliteng_ops)
[    4.060827] imx-drm display-subsystem: bound imx-drm-dpu-bliteng.5 (ops dpu_bliteng_ops)
[    4.070027] imx-drm display-subsystem: bound imx-dpu-crtc.0 (ops dpu_crtc_ops)
[    4.077586] imx-drm display-subsystem: bound imx-dpu-crtc.1 (ops dpu_crtc_ops)
[    4.085164] imx-drm display-subsystem: bound imx-dpu-crtc.3 (ops dpu_crtc_ops)
[    4.092735] imx-drm display-subsystem: bound imx-dpu-crtc.4 (ops dpu_crtc_ops)
[    4.099981] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bind] id = DSI0
[    4.100392] imx-drm display-subsystem: bound 56228000.dsi_host (ops nwl_dsi_component_ops)
[    4.109053] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1
[    4.116910] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_valid] Validating mode:
[    4.122367] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_valid] Validating mode:
[    4.122374] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_fixup] Fixup mode:
[    4.122378] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_fixup] lanes=4, data_rate=822000000
[    4.122493] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_valid] Validating mode:
[    4.122496] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_fixup] Fixup mode:
[    4.122500] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_fixup] lanes=4, data_rate=822000000
[    4.130178] Console: switching to colour frame buffer device 352x45
[    4.130206] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_valid] Validating mode:
[    4.130210] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_fixup] Fixup mode:
[    4.130213] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_bridge_mode_fixup] lanes=4, data_rate=822000000
[    4.143542] imx-drm display-subsystem: fb0: imx-drmdrmfb frame buffer device
[    4.151519] imx-rproc imx8qm_cm4@0: failed to find syscon
[    4.157065] imx-rproc imx8qm_cm4@0: mbox_request_channel_byname() could not locate channel named "txdb"
[    4.166487] imx-rproc imx8qm_cm4@0: No txdb, ret 0
[    4.171878] remoteproc remoteproc0: imx-rproc is available
[    4.177705] imx-rproc imx8x_cm4@1: failed to find syscon
[    4.183135] imx-rproc imx8x_cm4@1: mbox_request_channel_byname() could not locate channel named "txdb"

This is because pixel clock is too high, 137 MHz, which generates 137 x 6 (4 data lanes) the driving clock of 822 MHz. I guess, it can handle only up to 810 MHz.

Then, in this case these clocks from clk_summary are 0s:

a72_clk 0 0 0 1296000000 0 0 50000
a53_clk 0 0 0 1200000000 0 0 50000
mipi_pll_div2_clk 0 0 0 000000000 0 0 50000
mipi0_dsi_rx_esc_clk 0 0 0 000000000 0 0 50000
mipi0_dsi_tx_esc_clk 0 0 0 000000000 0 0 50000
mipi0_dsi_phy_clk 0 0 0 000000000 0 0 50000
mipi1_dsi_phy_clk 0 0 0 000000000 0 0 50000

Thank you,
Zoran


clk_summary.txt (43.3 KB)

Hi @_nobody !

Could you please specify which version of Apalis are you using? It it a Toradex Hardware?

Best regards,

I am for now using var spear development system… For i.MX8QX.

Best Regards,
Zoran


Hi @_nobody !

I see, but this Community and all Toradex support are limited to Toradex’s hardware.

Therefore, I am closing this topic.

If you are interested in Toradex’s products and support ( :wink: ), please check the NXP i.MX 8QM Computer on Module - Apalis iMX8, as it might fit your needs.

Best regards,