Hi! I’m trying to disable the KSZ9031RNX Ethernet Transceiver by setting MODE[3:0] pins to 0111 as per 2. As per 6 and 5, the mode pins are shared by the RGMII pins. I found the relevant portions of the device tree but I’m at a loss about how it works. Worth pointing out I assume that I need to modify the device tree but actually I don’t know. I tried to post everything below. Thank you so much!
What I tried
Inside imx6qdl-apalis.dtsi
changed
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 # I think this is pull up
to
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x130b0 # I think this is pull down
It’s worth noting that I check by directly probing the signals on the chip. Originally, MODE[3:0] = 0000. After this change, still MODE[3:0] = 0000. This means the change above did nothing.
#Resources
Apalis iMX6 Data Sheet.1
KSZ9031RNX Data Sheet.2
Device Tree Customization.3
Apalis iMX6 Device Tree.4
Relevant Question.5
iMX6 Processor Data Sheet.6
Device Tree Spec7
#imx6qdl-apalis.dtsi excerpt
/* PAD Ctrl Values for Common Settings */
#define PAD_CTRL_HYS_PU 0x1b0b0 /*(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
#define PAD_CTRL_HYS_PD 0x130b0 /*(PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
#define PAD_CTRL_PU_22k 0x0f058 /*(PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm)*/
#define PAD_CTRL_NO 0x80000000
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
#pinfunc.h excerpt
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
....
#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0
....
Update
So I learned how to update the device tree properly and verified that it was being installed.
Now mode = 1101
This is confusing to me though. I’ve pasted kernel.patch below. I only set RD3 to PAD_CTRL_HYS_PD.
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -286,7 +286,7 @@
phy-handle = <ðphy>;
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 25 1>;
- status = "okay";
+ status = "disabled";
mdio {
#address-cells = <1>;
@@ -682,10 +700,10 @@
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x130b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};