How to disable the DTR/DSR functionality in iMX8 UART 1

How can I disable the DTR/DSR functionality in UART 1? I have serial communications running on the M4 cores under freeRTOS, which runs as expected. However, when Linux boots it takes control of the M4.I2C0.SDA and M40.I2C0.SCL pins to use for DTR and DSR controls for UART1. Which are the TX and RX pins for the M4 UART.

I tried first just to delete the following lines from the device tree

//		/* Apalis UART1_ */
//		pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
//			fsl,pins = <
//				/* Apalis UART1_DTR */
//				SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06	0x00000021
//				/* Apalis UART1_DSR */
//				SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07	0x00000021
//				/* Apalis UART1_DCD */
//				SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10	0x00000021
//				/* Apalis UART1_RI */
//				SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11	0x00000021
//			>;
//		};

but now the serial console does not work.


HI @Andy.McClernon

Thanks for writing to the Toradex Community!

Could you make these changes to the devicetree file and check if this solves the issue?

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1.dtsi
index 6f5e5d9b62c2..3ad8a3345a68 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-v1.1.dtsi
@@ -412,7 +412,7 @@
        pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
                    <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
                    <&pinctrl_gpio34>, <&pinctrl_gpio_usbh_oc_n>,
-                   <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
+                   <&pinctrl_lvds0_i2c0_gpio>,
                    <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
                    <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
                    <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,

Best regards,

Sorry I should have mentioned that I already did that. The device tree did not compile before that.

I made these changes and compiled and flashed the device-tree to the SoM which is working fine.

Could you provide the version of the Software of your module?
How did you compile the device-tree file?

Best regards,

  • SCFW b929edfe, SECO-FW 27167ff2, IMX-MKIMAGE d7f9440d, ATF bb209a0
  • U-Boot 2018.03-toradex_imx_v2018.03_4.14.98_2.3.0_bringup+gd626574ba1
  • Linux version 4.14.170-3.0.4+gbaa6c24240a4 (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP PREEMPT Tue Apr 21 04:11:13 UTC 2020

The device tree was compiled using “make freescale/fsl-imx8qm-apalis-eval.dtb” after running “make defconfig”. Environment variables were ARCH=arm64 and CROSS-COMPILE=aarch64-linux-gnu.

Appreciate your help.

That dtb worked. It also solved the problem with the pins :slight_smile:

I noticed that your dtb is smaller than the file my toolchain produced.

Diff output is attached (it formatted all weird inline)link text


Thanks for the Information.

Could you share your changes ( git diff) ?
Additionally could you flash the attached devicetree and check if you still have the issue?
Which carrier Board are you using?

Best regards,

Perfect that the dtb file worked.

Which version of the Toolchain are you using? I am still using gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu.

Best regards,

I am using gcc-arm-8.2-2019.01-x86_64-aarch64-linux-gnu. Do you think that could be the problem?

No, other colleagues are using the version 8. For example 8.3-2019.03. This should work fine.

Best regards,

Please would you send me the original source from which you built that dtb. If the toolchain works then the source must be different.

Hello Andy

the sources are in my first answer. I just deleted <&pinctrl_lpuart1ctrl> in the regular source files. Nothing else.

Best regards,