How to change the edge of the pixel clock

Hi all,
due to a layout change we need to change the sampling edge of the pixel clock from falling to rising. I have tried to change the entry
pixelclk-active = <0>;
pixelclk-active = <1>;
in the kernel source file
However, this had no effect. I remember that with an older kernel (< 4.0) this change worked perfectly, but now there is no change in polarity.
I have also tried to change the vidargs variable to
setenv vidargs dcufb:pixclockpol:1,480x272-16@72,monitor=lcd
also with no change (I have also tried a ‘0’ behind the pixclockpol value.

Is there a way to change the polarity?
We are using a Colibry VF50 module with kernel 4.15

Thanks in advance

Hi Bernd,

I just changed the pixel clock polarity for the VGA resultion in the device tree for a 4.1.15 kernel, it seems to work fine here. Can you check if really the correct device tree get loaded, e.g. by validating the value from /proc:

root@colibri-vf:~# hexdump -C /proc/device-tree/soc/aips-bus\@40000000/dcu\@40058000/display\@0/display-timings/640x480/pixelclk-active 
00000000  00 00 00 01                                       |....|

Note that with the latest release, we provide a 4.4 kernel, which does not support the old display timing mechanism. Hence check that you really are using a kernel from the 4.1 series:

root@colibri-vf:~# uname -a
Linux colibri-vf 4.1.15-00193-gb8c0c77-dirty #13 Fri Apr 15 09:16:00 PDT 2016 armv7l GNU/Linux

Hi Stefan,
I have cross checked on a different system. There it worked as expected. I will have to check the hardware.