due to a layout change we need to change the sampling edge of the pixel clock from falling to rising. I have tried to change the entry
pixelclk-active = <0>;
pixelclk-active = <1>;
in the kernel source file
However, this had no effect. I remember that with an older kernel (< 4.0) this change worked perfectly, but now there is no change in polarity.
I have also tried to change the vidargs variable to
setenv vidargs dcufb:pixclockpol:1,480x272-16@72,monitor=lcd
also with no change (I have also tried a ‘0’ behind the pixclockpol value.
Is there a way to change the polarity?
We are using a Colibry VF50 module with kernel 4.15
Thanks in advance