Hi Team ,
We are tying to configure the SPI Controller registers from LINUX
For this we observed that the write operation (ioremap_nocache + writel ) to harwdare registers is taking approx 2.2 micro seconds .
We think that this oiperation should have taken much less time than 2.2 micro seconds to do an write operation from CPU to SPI Controller
Could team please let us know :-
a) Is there any standard / proven way by which we could reduce this time ?
b) Or is there any alternate way to complete the opeartion in much faster time ?
c) Will increasing the SPI Controller Core frequency help in any way ?
Would be helpful if you can please provide some pointers as to where could i look to achieve this .
Thanks ,
Ashish Kumar Mishra .
I’m really unsure as to what exactly it is that you are trying to achieve. Why exactly would you want to directly access any such registers and not use the Linux kernel’s built-in SPI stack?
Dear Marcel ,
We are doing an proof of concept w.r.t one of customer requirement.
The requirement is to capture the SPI sensor data of around 144bits
( 18bit sensor * 8 sensor ) . The timing we were trying is around 10-15us ( targetting 48 or 96k sampling rate )
With default driver we are getting the spi-read for around 110 to 220us . Hence we were looking for an way to achieve this data rates
Now we are evaluating usage of PCIe based solution .
The sensor data would be buffered on custom PCIe based card which the CPU can read at regular interval ( aim is interrupt based )
This approach we feel will meet our timing requirement without straining CPU , as the data buffering would be done by custom logic. Depending on the results , we would take an further call.
The last resort would be to actually by-pass the controller driver & build an custom spi-controller driver with support to specific case.
Hope i could explain the reason .
I would be thankful & would appreciate you valuable & experienced
comments / feedback / observation on this approach.
Thanks
Ashish Kumar Mishra
