GPIO Pin during uboot

I am trying to use pin SODIMM_101 as a GPIO. It needs to be pulled up at boot and stay high. I have read the following link.

I have attached a screen shot from a scope of what I am seeing.

  • CH2 is 3.3V connected at X37 pin 3.
  • CH3 is SODIMM_101 connected at X22 pin 7.
  • CH4 is RESET_OUT# connected at X3 pin B32.

I am also staying in uboot and not booting into Linux to ease the debug process.

Per the scope image, when Colibri SOM comes out of reset, it acts like I expect it to as the pad at reset is configured as an input and 100k pull-up. Then about 10ms later it goes low and stays low for around 120ms. After that uboot seems to then pull the pin up. I also have a “strong” 10k pull-up attached as an extra precaution.

The colibri_imx6.c file is attached and the pad is defined as WEAK_PULLUP on line 218. Do you know a reason why the GPIO pin is low for 120ms?



SODIMM_101 is connected to the i.MX 6’s ball EIM_ADDR17. After RESET that pin is muxed to the EIM_ADDR17 function which is an address output of the parallel bus outputting ‘0’.

There is nothing you can do to prevent this. You could shorten the time for which that ‘0’ is outputed by changing the pinmuxing earlier. The earliest would be to put the write to the muxing register into the DCD initialization sequence.

That can be accomplished as follows:

diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg
index e7886de..8077197 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.cfg
+++ b/board/toradex/colibri_imx6/colibri_imx6.cfg
@@ -25,6 +25,9 @@ BOOT_FROM      sd
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
+/* set the pinmuxing of SODIMM 101, EIM_A17 to GPIO */
+DATA 4, 0x020e0114, 0x05
 #include "ddr-setup.cfg"
 #if CONFIG_DDR_MB == 256

With that it takes around 30ms from RESET to the pin changing from 0 → 1.

Note that the bootrom which goes through the DCD table only allows to write to certain address regions. Notably the GPIO controller’s registers are not among them. So you can not change a GPIO to output or set its value.

Refer to ‘Table 8-33. Valid DCD Address Ranges’ in the i.MX6 reference manual for a list of the address ranges which can be written to from the DCD tables.


I am glad to see an answer even if it does mean I have to change my hardware a bit. I have looked in NXP’s datasheet for the iMX6SDL and did not find this information (although it is a big datasheet and probably missed it). I know how to find the ball/pad name and the default pad settings, but how would I know the EIM pins are driven low at boot? Where is this documented? I am wondering this as I change my hardware and wondering what some of the other pins are doing at boot that I have configured as GPIO.

That it is muxed in it’s EIM functions can be seen in the ‘Pad Mux Register
(IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17)’ sub chapter in the reference manual.

The data direction is specified in the recpective chapter of the muxed function, e.g. for EIM in ‘Table 22-2. EIM External Signals’.

If the initial state of the pin is specified I don’t know. In the EIM timing diagram the state is specified as ‘last valid address’.