Hey @crsl,
How are you doing with this?
The address you see @ the end of a node is set by the SoC. In this case we would have to go to NXP I.MX8X Application Processor Reference Manual to see what these would be. I believe this involves making a basic account and accepting the terms. But here is the link to get that started. https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true
If this link doesn’t work, you can search for IMX8DQXPRM in their search bar.
Take a look at LSIO Memory Map (table 2-4). You will see the memory addresses allocated for PWM.
We can also verify this with looking at our device tree includes…
imx8qxp-colibri.dtsi → includes imx8qxp.dtsi → includes “imx8-ss-lsio.dtsi”
which has information regarding our pwm pins…
In the node lsio_subsys, we find our lsio_pwm<0,1,2,3>
36 lsio_pwm0: pwm@5d000000 {
35 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
34 reg = <0x5d000000 0x10000>;
33 clock-names = "ipg", "per";
32 clocks = <&pwm0_lpcg 4>,
31 <&pwm0_lpcg 1>;
30 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
29 assigned-clock-rates = <24000000>;
28 #pwm-cells = <2>;
27 status = "disabled";
26 };
25
24 lsio_pwm1: pwm@5d010000 {
23 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
22 reg = <0x5d010000 0x10000>;
21 clock-names = "ipg", "per";
20 clocks = <&pwm1_lpcg 4>,
19 <&pwm1_lpcg 1>;
18 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
17 assigned-clock-rates = <24000000>;
16 #pwm-cells = <2>;
15 status = "disabled";
14 };
13
12 lsio_pwm2: pwm@5d020000 {
11 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
10 reg = <0x5d020000 0x10000>;
9 clock-names = "ipg", "per";
8 clocks = <&pwm2_lpcg 4>,
7 <&pwm2_lpcg 1>;
6 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
5 assigned-clock-rates = <24000000>;
4 #pwm-cells = <2>;
3 status = "disabled";
2 };
1
67 lsio_pwm3: pwm@5d030000 {
1 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
2 reg = <0x5d030000 0x10000>;
3 clock-names = "ipg", "per";
4 clocks = <&pwm3_lpcg 4>,
5 <&pwm3_lpcg 1>;
6 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
7 assigned-clock-rates = <24000000>;
8 #pwm-cells = <2>;
9 status = "disabled";
10 };
The second value in reg is reference to the size/increment between the pwm nodes.
lsio_pwm0: pwm@5d000000
lsio_pwm1: pwm@5d010000
lsio_pwm2: pwm@5d020000
lsio_pwm3: pwm@5d030000
So I believe the next two pwm pins would look like this:
pwm4: pwm@5d040000
pwm5: pwm@5d050000
The & is a reference to a node label. So if you don’t already have a pwm node, &pwm has nothing to reference.
You could then assign pinctrl nodes via the &pwm4 and &pwm5.
-Eric
