I’m working on trying to port M4 spi code to the A7. I got it to compile, but along the way, lost the interrupt that code needs. The interrupts are very different between the M4 and A7. As of today April 12 2017, I am trying to get user interrupts working on my build so I can add in an interrupt that I think is needed by the spi code I ported. Unfortunately, little support exists for using the second A7 processor or doing bare metal on the A7 cores. I’m happy to trade code with others working on this stuff erickrieg at gmail
Toradex does not support bare-metal or FreeRTOS on Cortex-A7 cores.
That said, some hints which might help you get further: The Cortex-M4 NVIC Interrupt controller support code comes from CMSIS and the FreeRTOS port itself. As you noted, A-Class core have a completely different interrupt controller called GIC. There seems to be some CMSIS implementation for A-class cores, see CMSIS-Core-A… It seems that FreeRTOS has A-Class support too, I am not sure how that ties to the interrupt controller, but it might be worth checking that, see Using FreeRTOS on ARM Cortex-A9 Embedded Processors and the
FreeRTOS/Source/portable/GCC/ARM_CA9 in the official FreeRTOS releases.